Combining RISC-V and FPGA Offers New Design Solutions

Jim Harrison for Mouser Electronics

(Source: Shutterstock/usk75)

Small, low power, high performance SOC FPGAs fit many applications to a T. 

The advent of the RISC-V instruction set has given the design engineer a solid basis for system design using an FPGA with a processor core and standard or custom extensions. The no-cost RISC-V instruction set is open and frozen, and processor designs and extensions will continue to work well, even as RISC-V evolves. In other words, this RISC-V processor is a no-risk proposition.

RISC-V-based processors are used for imaging and sensor interface, military and aerospace, Internet of Things (IoT), automotive and rail transportation, and industrial controls. RISC-V designs offer high-data throughput that is needed across several applications, including smart embedded vision, hybrid and electric vehicles, wireless communication infrastructure, and robotics. And the ease of running a real-time operating system, including Linux, makes for robust control systems design.

An FPGA is probably the best way to implement RISC-V processor-based designs. The engineer may choose a soft-core processor that is implemented using the FPGA fabric or a hard-core CPU that is physically implemented as a structure in the silicon during manufacturing. A soft core may offer a higher level of design reuse and reduced obsolescence risk, while the hard core is the performance champ.

FPGAs are great for implementing operations that are either very complex or time-consuming for general-purpose CPUs. Block ciphers and cryptographic functions, for example, are performed by CPUs using a great many cycles and requiring much more time than a specialized FPGA fabric available as a fully designed IP core.

Microchip offers RISC-V processing in two PolarFire families (plus one rad-tolerant type). Both offer processor options suitable for RISC-V implementation. All of the devices are non-volatile, instant-on. They have four to twenty-four optimized 12.7Gbit/s transceivers that are said to require 1/2 the power vs. competing products, plus DDR4 and 1.6Gbit/s LVDS interfaces. The chips offer a system controller suspend mode for safety-critical designs and many security features.

PolarFire MPFxxxT FPGAs come in 50k, 100k, 200k, 300k, and 500k logic element (LE) versions—with the option of a Mi-V RISC-V soft core processor. An essential CPU core uses up to about 10k LEs. The chips’ integrated hard IP includes a dual PCIe endpoint/root port, PLLs, DLLs, an 18 x 18 MACC pre-adder, and a crypto processor.

A few examples of the more than 100 available application-specific extensions would be a finite impulse response (FIR) Filter, a CRC32 (32-bit cyclic redundancy check), and 3DES (Triple Data Encryption Standard) algorithms. Adding extensions to a RISC-V core performance on these functions can be significantly accelerated while saving considerable power.

Figure 1: The 16 x 16mm package version of the PolarFire SOC. (Source: Microchip)

The hard-core PolarFire SOC (system-on-a-chip) versions (Figure 1) have five CPU cores—four processor cores and a monitor core—all of which are RV64 64-bit implementations. They come in five versions with 25k to 460k LEs (See Table 1). It's the first system-on-chip (SoC) FPGA with a deterministic, coherent RISC-V CPU cluster and a deterministic L2 memory subsystem that enables Linux and real-time applications.

Built on a state-of-the-art 28nm non-volatile process, PolarFire uses about half the power of other FPGA families. The PolarFire RISC-V CPU micro-architecture implementation uses a simple five-stage, single issue, in-order pipeline that doesn't suffer from the Meltdown and Spectre exploits found in standard out-of-order machines. All five CPU cores are coherent with the memory subsystem allowing a versatile mix of deterministic real-time systems and Linux in a single multi-core CPU cluster (Figure 2).

Table 1: The powerful five-core PolarFire SoC FPGAs come in five versions with package sizes from 11mm to 35mm square. (Source: Microchip)

These processors feature immunity to network-based security attacks that is not readily available in other cores/ISAs, especially when it comes to IoT applications. Instead of relying only on compartmentalization and communication security, RISC-V is unique. It includes computing security to stop buffer overflows and protect the processor from being overtaken by cyberattacks that arrive via the network and exploit vulnerabilities in the code.

With PolarFire technology offering 50% lower power (in many cases) than competing FPGAs, they can be used in small-form-factor environments, where removing heat is hard, or enable removal of fans from a system.

Figure 2: The PolarFire SOC system architecture.  (Source: Microchip)

The definition of a real-time system, in its simplest form, executes deterministically periodically. A real-time Linux OS requires a memory management unit (MMU) to virtualize physical memory without using branch prediction. The PolarFire SOC can support both of these requirements.

The chip's four RV64GC cores can run Linux, while the RV64IMAC monitor core cannot. The L2 memory subsystem is 2Mbytes in size with error correction and the ability to be configured into three modes: A 16-way set associative cache, a loosely integrated memory (LIM), and a scratchpad memory. LIM memory can be constructed in 128KB chunks and assigned exclusive access to a processor.

Libero® SoC Design Suite v12 offers easy-to-learn, easy-to-adopt development tools for designing with PolarFire. The suite integrates industry-standard Synopsys Synplify Pro® synthesis and Siemens ModelSim® simulation with best-in-class constraints management, programming and debug tools capabilities, and secure production programming support. The systems MSS Configurator is a tool to configure the PolarFire SoC CPU subsystem. It is used to configure MSS clocks, fabric interfaces, I/O banks, DDR memories, and debug features.

The HDL simulator is the critical tool for building the hardware architecture. It allows you to simulate how the architecture works when given sample input data.

Qualified customers can start designing without hardware with Microchip’s Libero SoC 12.3 FPGA design suite and SoftConsole 6.2 integrated development environment. They can also debug their embedded applications using Renode, a virtual model of the microprocessor subsystem.

The PolarFire SoC Icicle Development Kit (Figure 3) is a low-cost design platform that enables evaluation of the five-core RISC-V microprocessor device, innovative Linux, real-time execution, and the subsystem's low-power capabilities. The kit features the proper memories (LPDDR4, SPI, and eMMC flash) to run Linux off-the-shelf, including a power sensor to monitor various power domains, a PCIe root port, Raspberry Pi 4, SD card, and mikroBUS expansion ports, with USB, UART, CAN, and I2C wired connectivity options, and with Gbit Ethernet.

Figure 3: Quick PolarFire SOC design turns can be accomplished via the Icicle Design Kit. (Source: Microchip)

The Icicle Kit PolarFire SoC device is programmed using the onboard FlashPro6 programmer or an external FlashPro 4, 5, or 6 programmer. The 18.3cm x 12.6cm kit includes a 12V/5A wall-mounted power adapter, an Ethernet cable, a USB 2.0 micro connector for a UART interface to a PC, and a Quickstart card.

The designer faces less risk using a RISC CPU. For a wise design team, the RISC-V ISA could be used to establish an MCU framework that spans generations of devices and products. And for really demanding applications, the hard implementations with FPGA fabric and cores with vector extensions are becoming readily available.

The new way of doing things is to pick an instruction set first, then a core vendor, and lastly, add extensions as needed. Remember, RISC-V is not a core or a CPU. It is an instruction set specification. You can get a core that’s part of an FPGA or a core design from multiple open-source vendors (at least a dozen), or you can buy a core/processor from commercial core providers.