Why TOLL-8N Is Gaining Momentum in High-Power, High-Density Designs

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Published May 18, 2026

For electronic engineers, device packaging is just as critical to performance and thermal management as the die or multichip assembly it contains. This is especially true as gallium nitride (GaN) power devices continue to gain adoption, placing renewed emphasis on packaging as a key factor in unlocking their full performance potential. Even small parasitic elements—such as stray inductance, capacitance, and resistance within the package—can significantly affect circuits switching higher voltages and currents at faster slew rates. As a result, engineers cannot afford to overlook the importance of optimized packaging.

This blog examines why packaging is increasingly important for 650V GaN devices and how the innovative TOLL-8N package helps enhance the performance of high-speed, high-voltage field-effect transistors (FETs) while addressing parasitic effects and thermal limitations.

Start with LCR Basics

The impact of parasitics can be understood through a simple equation that defines the relationship between inductance (L) and the rate of change of current $\frac{{\mathrm{di}}^{\mathrm{}}}{\mathrm{dt}}$:

V (t) = L $\frac{{\mathrm{di}}^{\mathrm{}}}{\mathrm{dt}}$

The use of GaN FETs does not change the basic physics. However, their extremely fast current and voltage switching ($\frac{{\mathrm{di}}^{\mathrm{}}}{\mathrm{dt}}$) means that even small parasitic values once considered negligible can now have a pronounced effect on circuit waveforms. In actual hardware, these parasitics can lead to issues such as increased power-device drain overshoot and ringing, gate bounce that may cause false turn-on, and higher electromagnetic interference (EMI) peaks.

Such effects are often missed in simplified simulations. Accurate predictions typically require nonlinear device models or explicit extraction and inclusion of parasitic elements.

Identifying the locations, types, and values of all parasitics is no simple task. Although these parasitic values are very small, their impact on circuit behavior can be substantial. They are also difficult to physically access, measure, and verify.

Many of the most harmful parasitics arise from board layout, probing techniques, grounding, and copper geometry. While these elements lie outside the direct control of the power device itself, they strongly influence the measurement process. Further complicating matters is that many parasitic parameters are not fixed, as they are with discrete inductors or capacitors, but instead can vary depending on operating conditions such as drain-source voltage (V_DS).

What Changes at 650V Compared to Lower-Voltage Switching

As voltages rise from lower ranges, such as 80V to 200V and up to 650V, some design factors scale predictably while others do not. Higher power-rail voltages make devices more sensitive to overshoot, since there is less margin as the voltage approaches the V_DS rating. At the same time, faster switching speeds and sharper edges increase the voltage induced by $\frac{{\mathrm{di}}^{\mathrm{}}}{\mathrm{dt}}$ across any inductance. As a result, gate-drive techniques that may be sufficient at lower voltages cannot simply be scaled up–as device behavior changes with voltage and current.

Package parasitics set a practical upper limit on power-device performance. Just a few nanohenries (nH) of DC-link or commutation loop inductance can interact with circuit capacitances to produce ringing and drive V_DS into potentially destructive overshoot during turn-off. In addition, common-source inductance (CSI) can distort the gate-source voltage (V_GS), while gate-loop inductance feeds back to alter the effective input impedance seen by the driver, distorting the driver-current waveform.

The effects of fast dv/dt slewing can be especially problematic because they pump current through the power FET’s Miller capacitance. If the gate feedback loop has a loose time constant, which is often necessary for functional reasons, brief gate-source glitches may be enough to trigger shoot-through.

Rapid $\frac{{\mathrm{dv}}^{\mathrm{}}}{\mathrm{dt}}$ creates displacement current through the gate-drain (Miller) capacitance. If the off-state gate path impedance is too high, or if CSI raises the source potential, the gate of the complementary switch in a half-bridge can momentarily exceed the threshold voltage and cause false turn-on. This leads to shoot-through, a condition where both the high-side and low-side FETs conduct simultaneously, creating a low-impedance path directly from the power supply to ground. The resulting high-current spikes are severe enough to damage or destroy the switches.

Go Kelvin

Engineers familiar with high-precision test and measurement understand the value of four-wire Kelvin connection. This technique is used to eliminate measurement error caused by voltage drops from current flowing through wires and other resistive elements connected to the device under test (DUT).

In a Kelvin configuration, two conductors supply current to and from the DUT, while a second pair connects directly to the DUT terminals to sense voltage. Because these sense leads carry virtually no current, they experience no resistive voltage drop, allowing for more accurate voltage measurement (Figure 1).

A variation of the four-wire Kelvin connection is used in many power GaN packages to improve switching performance. In this implementation, an additional Kelvin source lead is included to provide a dedicated, low-return path for the gate-drive circuit. By isolating the gate-source sensing path from the high-current power source return, this approach enables more precise control of the power device.

Figure 1: Schematic diagram of a power MOSFET with Kelvin source. (Source: ROHM Semiconductor)

Using a Kelvin connection minimizes the inductive voltage fluctuations that would otherwise occur in the primary current-carrying path by decoupling the gate-drive return from that path. This significantly reduces CSI that would otherwise appear as negative feedback on the gate signal. Such feedback is detrimental because it opposes the action of the gate driver, increasing switching losses and potentially contributing to oscillation.

Packaging Impacts on Cooling

If minimizing package and printed circuit board parasitics were the only concern for device designers, the challenge would be more straightforward. However, packaging must also serve as the thermal pathway, conducting heat from the internal die to the external environment where it can be dissipated and removed.

Cooling is typically accomplished by some sort of heat-sink structure that draws heat away from the localized source. This is often supplemented by natural convection or forced-air cooling, such as a fan, to further reduce temperature within the board and enclosure. As with parasitic effects, the thermal behavior of an integrated circuit (IC) die within its package can be complex and requires careful consideration.

Several factors influence heat flow and dissipation, but designers typically begin by focusing on two key parameters:

• θ_JC: Thermal resistance from the die junction to the case. This is often divided into case-top and case-bottom values, making it a useful first-order metric for comparing different package options.
• θ_JA: Thermal resistance from the junction to ambient, often separated into top and bottom paths and represents the resistance from the package case to the surrounding air. It is especially important when evaluating convection cooling and, unlike θ_JC, does not include an external heat sink.

Minimizing parasitics and thermal resistance are closely linked aspects of package design. For example, flip-chip construction can reduce the wire bonding impedance to improve efficiency while also lowering thermal resistance from die to IC pins. Larger solder paste areas and lead-frame structures can provide similar benefits, although these improvements may be limited by overall package constraints.

Once heat reaches the outside of the package, additional design measures can further improve dissipation. These include increasing copper area and thickness under and around the package, adding thermal vias to spread heat to other PCB layers, and attaching heat sinks directly to the package.

TOLL-8N Package Makes a Difference

The choice of power device packaging has a considerable impact on PCB layout and can strongly influence package-to-board parasitics. To address the growing need for both lower thermal resistance and package parasitics, power device vendors are adopting advanced package technologies.

One example is the TOLL-8N surface-mount package used for ROHM Semiconductor’s GNP2070TD-Z, a 650V enhancement-mode GaN high-electron-mobility transistor (HEMT) (Figure 2). The device offers 70mΩ on-resistance and 5.2nC gate charge in a compact 11.68mm × 9.9mm × 2.4mm package, making it ideal for high switching-frequency and high-density converter applications.

Figure 2: ROHM’s GNP2070TD-Z 650V enhancement mode GaN HEMT, featuring the TOLL-8N package and contact layout. (Source: ROHM Semiconductor)

The 8-lead surface-mount TOLL-8N (TO-Leadless) package (Figure 3) provides shorter current paths and lower lead inductances than through-hole devices. Along one edge, eight terminals are arranged to support three functions: one gate contact, one dedicated Kelvin source contact, and six source contacts. Distributing the source connection across six leads reduces parasitics, current density, and thermal resistance. On the opposite edge, a single wide drain contact provides similar electrical and thermal benefits.

Figure 3: Cross-section of the internal connections of the GNP2070TD-Z package. (Source: ROHM Semiconductor)

TOLL-8N is one of several package options used for power devices. Other common types include the surface-mount DFN8080 and through-hole TO-247. Table 1 compares the key attributes of these three packages against major design-in criteria.

Table 1: Relative comparison of key package attributes for TOLL-8N, DFN8080, and TO-247 power-device packages. (Source: ROHM Semiconductor)

Conclusion

As power devices push towards higher voltages, currents, and performance levels, driven largely by advances in GaN technology, package parasitics and thermal characteristics are becoming increasingly critical to unlocking the devices’ full capability. Packages such as TOLL-8N reduce these detrimental effects compared to conventional alternatives. As a result, switching devices like ROHM Semiconductor’s GNP2070TD-Z, a 650V enhancement mode GaN HEMT, benefit from the capabilities of the TOLL-8N package to maximize performance.

Bill Schweber is a contributing writer for Mouser Electronics and an electronics engineer who has written three textbooks on electronic communications systems, as well as hundreds of technical articles, opinion columns, and product features. In past roles, he worked as a technical website manager for multiple topic-specific sites for EE Times, as well as both the Executive Editor and Analog Editor at EDN. At Analog Devices, Inc. (a leading vendor of analog and mixed-signal ICs), Bill was in marketing communications (public relations); as a result, he has been on both sides of the technical PR function, presenting company products, stories, and messages to the media and also as the recipient of these. Prior to the MarCom role at Analog, Bill was associate editor of their respected technical journal, and also worked in their product marketing and applications engineering groups. Before those roles, Bill was at Instron Corp., doing hands-on analog- and power-circuit design and systems integration for materials-testing machine controls. He has an MSEE (Univ. of Mass) and BSEE (Columbia Univ.), is a Registered Professional Engineer, and holds an Advanced Class amateur radio license. Bill has also planned, written, and presented online courses on a variety of engineering topics, including MOSFET basics, ADC selection, and driving LEDs.