the outbound transmission of the frame through the transmit
queue, through the PHY, and back out onto the wire. This path
does not exist on a line-end node, as shown. Cut-through packet
switching is assumed here, rather than store-and-forward, which
has much higher latency as the entire frame is clocked into the
switch before it is forwarded.
The delay elements of the frame (Figure 5) are along a timeline,
where the total frame transmission time through one axis node is
illustrated. TBW represents the bandwidth delay, while TL_1node
represents the latency of the frame through a single node. Apart
from delays related to the physical transmission of the bits over
Figure 4: Frame latencies: (a) 2-port node frame latencies and (b) line end node. (Source: Analog Devices Inc.)
Figure 5: Frame transmission timeline. (Source: Analog Devices Inc.)
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5
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Industry 4.0 and Beyond | ADI
the wire and the clocking in of address bits for destination address
analysis, PHY and switch component latencies are the other elements
that impact the transmission delays within the system. As the bit rates
on the wire increase and the node count expands, these latencies
become even more important in the overall end-to-end frame
transmission delays.
ADIN1300 10/100/1000
Gigabit Ethernet PHY
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