| 4 | | 24 |
Figure 5: Vitis Application Development Flow optimizes the algorithm using SW and HW emulation in
the programmable logic before creating the final boot image. (Source: Author)
Figure 6: Vitis Analyzer Platform View helps developers identify the potential areas for optimizing
the kernel code. (Source: Author)
The RFSoC, combined with Vitis' OpenCL
capabilities, provides the developer with a
groundbreaking, tightly coupled solution. This
solution can provide the most responsive and
deterministic solution by leveraging high-level
languages, libraries, and frameworks. This
development methodology enables a higher level,
system-driven approach to solution implementation,
which results in a reduced time to market.
CONCLUSION
Once the software algorithms are implemented, the
developer can use the software and hardware emulation
flows provided by Vitis to optimize the algorithm for
implementation in the programmable logic before
generating the final boot image
(Figure 5).
To leverage the programmable logic's parallel nature, the
developer might want to pipeline or unroll loops, organize
memory, and AXI interfacing structures in the kernel.
These optimizations are implemented using pragmas
within the source code. Identifying the potential areas for
optimizing the kernel code can be performed using the
Vitis Analyzer and Vitis HLS analysis view
(Figure 6).
Once the optimization has been completed, the developer
can build the final boot files and deploy the system for the
next stage of testing and verification.
