Issue link: https://resources.mouser.com/i/1437750
| 9 | RADAR Reimagined Using the RFSoC Since its invention in the years immediately before World War II, RADAR (short for RAdio Detection And Ranging) has played a significant role in several applications. RADAR has been used within the defense arena for navigation, target detection, classification and tracking, missile guidance, and, thanks to synthetic aperture RADAR, even imaging. Outside of its military applications, RADAR has been used to provide safe navigation for air and sea traffic and monitor weather patterns for early warnings of approaching storms, typhoons, and hurricanes. Along with the jet engine, RADAR technology is one of the key technologies that has shrunk the world and enabled mass commercial air travel. RADAR is increasingly being deployed in automotive solutions, where it helps vehicle manufacturers achieve operation at the higher SAE levels of autonomy. Modern automotive RADAR is often referred to as 4D RADAR because it provides a large field of view, fine spatial resolution, and long-range performance. These capabilities enable RADAR to support autonomous operations such as traffic jam assist, highway driving, and self-parking. Regardless of the application, domain defense, civil, or automotive RADAR solution developers face several common challenges. These challenges relate to increased performance demands and Size, Weight, Power, and Cost (SWaP-C) reduction demands. Being able to implement smaller, more compact RADAR modules supports the development of phased array RADAR. Smaller modules enable the sub-elements of the phased array to be spaced at /2 to prevent interference. Addressing the Challenge A traditional approach to these SWaP-C and performance challenges has been the tighter integration of the high- performance analog-to-digital (ADC) and digital-to-analog (DAC) converters with a field-programmable gate array (FPGA) and processor. Such a discrete approach brings its implementation challenges, however. The discrete ADC/DAC and selected digital processing require increased board space because of the components themselves and the additional supporting components. The analog front end supports the ADC and DAC. Such an approach also needs to accommodate the JESD204B routing, which connects the ADC/DAC converters with the digital processing, further increasing the required board area. Design risk also increases with a discrete approach because the multi-gigabit per-second data rate of the JESD204B serial links performance depends significantly on the signal integrity of the routing, PCB material, and stack up. The discrete solution requires increased power dissipation in addition to the increased size of the board. One significant driver of the increased power dissipation comes from the transceivers needed to drive signals off the chip to connect downstream processing elements.