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| 4 | | 10 | The Xilinx Radio Frequency System-on-Chip (RFSoC), with its monolithic integration of multi-gigasample ADC/DACs, processing system, and programmable logic, enables system developers to address the SWaP-C challenges and achieve the performance demands. This monolithic integration creates a tightly integrated solution that enables a significantly reduced footprint and power dissipation, typically in the range of 50 percent to 75 percent. The integration of ADCs and DACs is not sufficient to address the challenges presented by many RADAR systems on its own. To fully address these, we must also integrate additional analog front end and clock distribution networks. To support this, the RFSoC also contains mixers, numerically controlled oscillators, and can correct gain and phase, along with supporting signals in either real or in-phase and quadrature formats. Such an approach, coupled with the RFSoC digital up and down converters subsystems, enables the RFSoC to use a direct sampling approach to minimize the required number of external components. This ability to support direct sampling allows one RFSoC solution to be configured for a range of different frequencies and signal bandwidths as needed by application or regulatory constraints. Such an approach also reduces temperature, tolerance, and aging effects on sensitive analog components. Of course, it is not just the ability to generate and sample RF signals using the RF-ADC and RF-DAC that enables the correct implementation of a RADAR system. The system also needs to communicate with other system elements to either configure the RADAR or report RADAR tracks. To aid in this process, the RFSoC contains a processing system (PS) consisting of a quad-core Arm ® Cortex ® -A53 64-bit Application Processing Unit and a dual-core Arm ® Cortex ® -R5 32-bit Real-time Processing Unit. This enables both real-time control and safety applications, along with high-performance applications, to be implemented within the RFSoC PS. Developing an RFSoC Solution The development of the RFSoC uses the Vivado IP Integrator flow to configure the RF elements as required. The signal processing algorithm can then be developed using traditional signal processing methods such as IP blocks created using High-Level Synthesis (HLS) or existing library IP components. In this approach, the software for the processing system is developed separately using Vitis and PetaLinux. Within Vivado IP Integrator, we can use the programmable logic to implement RADAR elements such as the chirp generation or beamforming and a resulting signal processing pipeline, including 2D-FFT, constant false alarm RADAR (CFAR), and location extraction. Programmable logic enables a parallel implementation of the algorithm resulting in the implementation offering a low-latency response and increased determinism. Supporting the low-latency solution is the availability of configurable logic blocks within the programmable logic and dedicated digital signal processor (DSP) elements, and diverse memory storage arrangements from distributed RAM to Block RAM and UltraRAM. The RFSoC family of devices provides between 3,145 and 4,272 dedicated 48-bit DSP elements, distributed within the programmable logic region. These DSP elements are designed to support implementations of Fast Fourier Transform (FFTs), systolic and multi-rate finite impulse response FIR filters, Cascaded Integrator-Comb (CIC) filters, and both real and complex multipliers and accumulators. If a 48-bit resolution is not required, the designer can leverage the single instruction, multiple data (SMID) operation mode and perform dual 24-bit operations or quad 12-bit operations. Figure 1: Traditional vs. RFSoCs tightly integrated approach. (Source: Xilinx)

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