Issue link: https://resources.mouser.com/i/1437753
12 Signal Chain Design Poses Difficult Challenges Filter modeling and simulation are of particular importance because higher frequencies, wider bandwidths, and resulting higher speeds create the potential for more crosstalk and signal noise. Modeling and simulation can take quite a bit of time, but the resulting information is invaluable in being able to easily identify signal imperfections—and isolate what adjustments are needed—before the system is physically built. Finally, signal chain testing is expensive and time-consuming. As a starting point, companies need to upgrade or develop testing equipment that is compatible with 5G. In addition to standard measurement functions, test systems also require specialized functions to determine RF signal characteristics. These upgrades and development can cost as much as 30 percent of the overall project. That said, the need for testing has never been higher because 5G only makes design more elaborate. ADI eases signal chain design by staffing RF semiconductor engineers who work at the silicon level and by: • Offering a "beams to bits" signal chain solution for mmWave 5G that offers the highest level of integration to reduce design requirements and complexity. Available only from ADI, this solution combines ADI's advanced beamformer IC, up/down frequency conversion (UDC), and additional mixed signal circuitry. • Providing software-defined and frequency-scalable platforms that reduce the number of product variants needed, reduce system complexity and cost, and decrease time to market. • Building more signal processing algorithms into products that optimize cost and power at the system level. • Providing multiple signal chain solutions from the antenna all the way to bits for sub-6GHz and mmWave applications. • Providing single platform SoCs that include several amplifiers and filters. • Providing highly sensitive test kits for modulating select frequencies. '' Unconsidered parasitic elements are likely to shift performance of high-frequency designs. Advanced modeling of interconnection and vias will help reduce design iterations." Jay Kruse Head of Hardware, eero