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| 4 | | 23 | hardware and software configuration of the underlying hardware. The hardware platform is created using the Vivado Design Suite, makes available clocks, Advanced eXtensible Interface processing system/programmable logic (AXI PS/PL) interfaces, and interrupts the Vitis compiler. Using these interfaces, the Vitis compiler can connect the acceleration kernels into the processing system memory map. This allows for efficient data transfer using Direct Memory Access (DMA) and control of the kernels. The platform's software element is provided by PetaLinux and provides an embedded Linux operating system that supports the Xilinx Run Time (XRT) (Figure 3). Of course, the base platform developed in Vivado can also contain design elements and the hooks available to Vitis. In the case of the Zynq UltraScale+ RFSoC, the base design can include the necessary infrastructure to connect the RF Data Converters to external interfaces using the GTY transceivers or transferring data to and from the processor memory space. Vitis Acceleration Once the acceleration platform is available, developers can begin to develop their solution using Vitis. Using Vitis, they can implement control and configuration of the RF data converters and additional internet protocol (IP). The developers can then also implement the desired RF data-processing algorithm using C/C++ and OpenCL C to accelerate through bottlenecks and improve overall system performance. To aid with the development of the algorithm, Vitis provides several open-source acceleration-ready libraries (Figure 4). These libraries include support for math, linear algebra, DSP, data compression, and, of course, AI. Figure 3: The Zynq UltraScale+ RFSoC Block Diagram outlines the solution structure. (Source Xilinx) Figure 4: The Vitis Development Environment provides open-source acceleration-ready libraries to aid in designing solutions. (Source: Author)

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