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| 4 | | 15 | convertor, each ADC has thresholding, quadrature modular correction (QMC), digital down converter (DDC), mixer, a numerically controlled oscillator (NCO), and decimation features. To transmit signals from the programmable logic using the RF-DAC, both digital and analog elements exist in the RF-DAC. However, the first stage in the transmission process is digital processing, which provides interpolation, mixer with NCO, quadrature modulation correction, and delays and output filters. The analog stage takes the digital output vector and converts it to an analog representation. Including diverse additional hard macro digital capabilities enables a more flexible, high-performance RF section versus implementing equivalent functions within the programmable logic. Within the RFSoC, the ADC and DAC are arranged in tiles. Each tile consists of several converters along with a phase-locked loop (PLL). In development, all tiles are configured using the RF Data Convertor IP blocks within the programmable logic. RF-ADC Two different ADC tiles, either a dual or quad tile, are within the RFSoC families. Notably, the type of tile does not define the number of convertors but instead, the configuration. Along with the RF-ADC convertor, each tile contains a PLL and clock network common to all convertors on a tile. A quad tile contains four RF-ADCs arranged as two pairs. Each of the converters can be configured for real input signals or as a pair for in-phase and quadrature (I/Q) signals. Although a dual tile contains two RF-ADCs, it can be arranged individually for real input signals or as a pair for I/Q signals. Every RF-ADC has its own differential analog input buffer capable of receiving full-scale signals of 1V peak to peak. Internally the differential input presents a 100 termination. The RF-ADC input is capable of being AC or DC, coupled if an active input is used. When the RF-ADC is AC coupled, the common-mode voltage does not have to be set. However, when the RF-ADC is DC coupled, each tile provides two VCM output voltages to assist the downstream active electronics in aligning the common- mode voltage. Should any signals exceed the input's full-scale range, each RF-ADC has built-in detection and protection for over range and over-voltage conditions. Over-range conditions are indicated by saturation, and a sticky over- range flag is raised. If an over-voltage event occurs, it is automatically shut down to protect the input buffer, and an over-voltage indication is generated to alert the user (Figure 1). Figure 1: RF ADC Input Range and Error Flags. (Source: Xilinx)

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