| 4 | | 21 |
system-level advantages as these analog front ends
are not programmable or readily adaptable to support
licensing or geographic restrictions, which often require the
use of different frequency bands.
The Zynq UltraScale+ RFSoC also contains a 64-bit quad-
core Arm
®
Cortex
®
-A53 Application Processing Unit and a
32-bit dual-core Arm Cortex-R5 Real-time Processing Unit
(Figure 1).
Real-time control and safety applications, and high-
performance applications, can be implemented within
the Zynq UltraScale+ RFSoC processing system (PS).
To support interfacing, the Zynq UltraScale+ RFSoC
PS also provides support for multiple industry-standard
interfaces, such as GigE, SATA, USB3, PCIe, CAN, I
2
C,
SPI, and more. At the same time, the programmable logic,
combined with the GTY Serializer/Deserializer (SERDES),
provides the ability to support all Common Public Radio
Xilinx PRODUCT SPOTLIGHT
ZYNQ ULTRASCALE+
RFSOC EVALUATION
TOOL DEMO
s
Interface (CPRI) line rates and up to 100GE.
Development of RFSoC solutions will strive to leverage
the programmable logic to benefit from the throughput,
determinism, and responsivity provided by its parallel
structure. Of course, solutions implemented using a
Zynq UltraScale+ RFSoC will be complex. Software-
defined radios, RADAR, and test equipment are excellent
examples. Developing and implementing these algorithms
purely at the register-transfer level (RTL) can be very time
consuming and impact the time to market.
One method that enables an optimal time to market while
still allowing the developer to leverage the parallel nature
of programmable logic is to use the Vitis unified software
platform from Xilinx. Vitis enables users to accelerate
algorithms from the processing system into the programmable
logic. This acceleration is made possible because of high-
level synthesis and OpenCL when working with Xilinx
heterogeneous system-on-chip devices or acceleration cards.
Figure 1: The Zynq UltraScale+ RFSoC Block Diagram outlines the solution structure. (Source Xilinx)
