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| 4 | | 5 | Figure 2: RFSoC RF-ADC. (Source: Xilinx) Benets of a Single-Chip Solution The traditional approach to tighter integration is the combination of multi-giga-sample ADCs and DACs with a field-programmable gate array (FPGA). This approach allows the FPGA to implement the ADC/DAC interfaces and signal processing pipeline. However, such an approach requires significant board space to implement the FPGA and its supporting peripherals and the analog front end containing the DAC and ADC. To address the increased operating RF-bandwidths, many data convertors implement interfaces that use JESD204B. These multi- gigabit serial link interfaces bring with them multiple issues in the design. JESD204B interconnects take FPGA resources and increase the solution's power dissipation. These JESD204B serial links also consume significant PCB areas to route multiple serial links and observe these high-speed links' signal integrity requirements. This distributed solution, therefore, presents an increased power dissipation that typical high-performance ADCs might require 2.25W. At the same time, DACs would require 1.75W in addition to the power dissipation of the JESD204B transceivers. This increases the board space required and increases the overall solution's power dissipation, thereby adversely impacting the size, weight, power, and cost (SWaP-C). The additional steps required to design the solution increases the time for development. This, therefore, increases the non-recurring engineering (NRE) and development costs and manufacturing, and bill of material costs. The RFSoC is a disruptive technology, which for the first time, creates a monolithic SoC that integrates the multi- giga-sample ADCs and DACs within the same silicon. Along with the ADCs and DACs, the SoC also contains a processing system and programmable logic. This creates a tightly integrated solution, providing a significantly reduced footprint and power dissipation, typically in a 50 percent to 75 percent reduction range. Integration of ADCs and DACs is not sufficient on its own to address the challenges presented by many RADAR systems. Let us look in-depth at the RFSoC and explore the capabilities it offers the RF system developer. RF Data Converters At the heart of an RFSoC is transmitting and directly receiving RF signals using the RF-ADCs and RF-DACs. Depending upon the generation of RFSoC, three generations of converters provide bandwidths of 4GHz, 5GHz, or 6GHz. These RF converters can be sampled at up to 5GSPS for the RF-ADC and 10GSPS for RF-DAC. This wide bandwidth combined with high sample rates allows direct sampling of L, S, C, and partial X band by leveraging the different first and second Nyquist zones. However, being able to sample the analog signal is the only aspect of converting and working with the received RF signal. The RF data converter block with the RFSoC offers several additional processing elements that can be leveraged by the designer to process the RF signal. The RF-ADC can be split into two distinct elements. The first element is the analog front end, which takes a differential analog input and converts the analog signal into a corresponding digital value. Following the analog value conversion to a digital representation is the digital element of the RF-ADC. This digital element contains thresholding, Quadrature Modular Correction (QMC), Digital Down Converter (DDC), Mixer and Numerically Controlled Oscillator (NCO), and decimation features. The output from the RF-ADC to the programmable logic is a 128-bit AXI Stream.

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