Supplier eBooks

| 4 | | 6 | SD-FEC No communication link is perfect, and as such, corruption can occur because of noise or unreliable connections. If no error correction is deployed, a corrupted packet is received each time it must be re-transmitted. Implementing this forward error correction enables the receiver to be able to correct for any corruption in transmission. To enable RFSoC communication links to implement FEC solutions, the RFSoC implements a Soft Decision-Forward Error Correction (SD-FEC) as hard macros within the programmable logic. Implementing the SD-FEC as a hard macro in the programmable logic provides the developer with significant advantages over an implementation using programmable logic. A hard-macro implementation enables a substantial power reduction and frees the programmable logic resources to implement the system- level algorithms. Within the RFSoC, SD-FEC implementations are controlled using AXI-Lite with data input and output using AXI Streams. This enables the SD-FEC to be easily integrated with the RF data converters and custom-developed algorithms. Programmable Logic Signal processing and signal generation algorithms will be implemented within the programmable logic. The creation of signal processing and generation algorithms can leverage the Xilinx IP library, especially when the design is implemented using the IP integrator within the Vivado ® Design Suite. These IP library components include filters, discrete Fourier transform (DFT) and fast Fourier transform (FTT), along with modulation components. If the required functionality is not available, the developer can implement their solution using either a pure Register Transfer Level (RTL) or increasingly high-level synthesis (HLS). HLS enables the developer to implement algorithms and functions in programmable logic defined in C or C++. High-level synthesis allows the developer to benefit from the increased verification time using C simulations, which are untimed, unlike RTL. This ability to simulate at a higher level, along with the productivity provided by developing in a higher-level language, can significantly reduce development time and increase portability. To support the RTL and HDL functions' implementations, the programmable logic provides several resources in addition to the traditional Look Up Table (LUTS) and Flip Flops. This includes the DSP48 elements used to implement multiplication and multiply-accumulate operations. The ability to store samples or waveforms is also crucial in both the signal processing and generation chain. Both Block RAM and UltraRAM provide storage elements. Block RAM is smaller and more configurable, while UltraRAM is extensive and enables the storage of a significant number of samples. The programmable logic can also support high-bandwidth I/O, enabling the RFSoC to connect to the wider external world using Interlaken, 100G Ethernet, 33G SerDes, or PCIe Gen 4. Such interfacing capabilities enable the high- bandwidth data required and generated by the RFSoC to be effectively moved on and off the chip. Processing System Such a complex RF and programmable logic solution requires tightly coupled sequential control. This is provided within the RFSoC by the processing system. The processing system is a complex heterogeneous system on its own. It contains three diverse processor types, with the main element being the Application Processing Unit (APU), which includes 64-bit quad-core Arm ® Cortex ® -A53 processors. The APU is intended to run embedded Linux Xilinx Zynq ® UltraScale+ ™ RFSoC ZCU111 Evaluation Kit Xilinx Zynq ® UltraScale+ ™ RFSoC ZCU216 ES1 Evaluation Kit Learn more > Learn more > Learn more >

• Cover