Issue link: https://resources.mouser.com/i/1447260
Würth Elektronik 2022 21 Figure 1: Overview of a HV half-bridge control of the High-side & Low-side SiC-MOSFET. (Source: Würth Elektronik Group) Figure 2: High ∆I/∆t current paths on turn-ON of SiC/GaN FET. (Source: Würth Elektronik) Figure 3: High ∆I/∆t current paths on turn-OFF of SiC/GaN FET. (Source: Würth Elektronik Group) Overview and Requirements for Gate Control In applications using SiC/GaN high-voltage semiconductor devices under hard- switching operation, galvanic isolation is a common requirement for safety and functional reasons. Depending on the application, a basic or a reinforced insulation will be required. The operating voltage, insulation material, pollution degree, and the applicable regulatory standards set the minimum creepage and clearance distances as well as the dielectric isolation voltage requirement affecting the components placed across the isolation barrier. The high-speed isolated gate driver integrated circuit (TI UCC21520) and the transformer in the isolated auxiliary power supply (DC/DC Block in Figure 1) both bridge this isolation barrier, leading to stringent safety and functional requirements. Some of the latest SiC-MOSFET devices require typical gate voltages of +15V for full turn-on and -4V for reliable turn-off. For a GaN-FET usually only +5V and 0V are required respectively, although a small negative voltage can also be applied to ensure turn-off in presence of excessive gate voltage ringing. Note that these values can vary depending on manufacturer. In Figure 1, a half-bridge configuration is shown, and several of these stages are typically required in an inverter circuit to drive AC motors in the kW range. Each SiC/GaN FET would require an independent gate driver stage with its own isolated auxiliary supply. This enables individual control of each SiC/GaN device and helps keep the gate current loop small and local to the device, minimizing the adverse effects of parasitic loop inductance and ground bounce caused by the very high ∆I/∆t generated during the switching transition (Figure 2 and Figure 3). Fast switching together with high operating voltages and increasing switching frequencies present important challenges to the gate driver system. "