Having a central PCIe bus
allows a very high-throughput
interface that could connect
two systems. You still may have
separate buses downstream
in the system, but their size can
be trimmed into something much
more manageable and lower risk."
C h a p t e r 2 | I n t e r c o n n e c t D e s i g n a n d S i g n a l I n t e g r i t y i n P r a c t i c e
Once engineers route the design, post-layout
simulation helps verify actual routing decisions.
Engineers can use techniques such as eye-diagram
and bathtub-curve analysis to identify hot spots or
marginal channels that could fail at speed, allowing
them to address issues long before fabrication.
Beyond software, designers should validate
assumptions on the benchtop. System-level
evaluation kits offer a way to characterize full signal
paths using real connectors and materials. This
step is especially important for reducing risk in
custom designs that deviate from standard PCI-SIG
reference channels.
Finally, OEMs should collaborate closely with
interconnect manufacturers, silicon vendors, and
system integrators to ensure the physical layer
behaves predictably. Leveraging a manufacturer's
shared reference designs can help design teams
avoid common bottlenecks in grounding, via design,
and breakout patterns.
Jesse Hawkins
Hardware Design Engineer,
Tektronix
17
8 Experts Discuss PCIe for Emerging Embedded Systems
