When designing for PCIe signal
integrity, the golden rule is to
maintain continuous impedance
and minimize stubs."
C h a p t e r 2 | I n t e r c o n n e c t D e s i g n a n d S i g n a l I n t e g r i t y i n P r a c t i c e
careful choices at advanced speeds. Engineers often
need lower-loss dielectrics to reduce attenuation and
preserve eye height at long trace lengths. Selecting
the right PCB stackup is, therefore, a significant
design decision.
Connector geometry also influences channel
performance when embedded systems use dense
layouts or constrained board shapes. Because PCIe
card-edge connectors use standardized mechanical
layouts, engineers can follow established breakout
patterns and routing rules for predictable loss
budgets per PCIe specification. However, embedded
systems frequently depart from these standardized
geometries and create routing paths that don't
match PCI-SIG's reference channels.
In these custom designs, breakout regions need to
be optimized via fields, strong ground stitching, and
careful launch tuning. Poor optimization can cause
reflections and degrade the channel before it even
reaches its first retimer or switch. Additionally, pitch
density impacts insertion loss and the allowable
trace width and will often force tighter signal
integrity windows in compact modules.
José-Augusto Moreno Escobar
Principal Hardware Engineer,
Visteon Corporation
15
8 Experts Discuss PCIe for Emerging Embedded Systems
