7
This filtering is done with capacitors and ferrite beads. If we have a touchy interface,
such as an analog-to-digital converter or phase-locked loop (PLL) component, we
will use a specific ferrite bead as a reference for the simulation. If this exact ferrite
bead does not come on the PCB, we can have a problem, such as a noise issue on the
PLL. Having accurate modeling data for capacitors is challenging because they are
not perfect components. They have parasitic characteristics that must be accounted
for in the simulation.
The trend toward smaller, denser designs will continue to push innovation. We are
seeing more stacking of die on die in IC packages. Maybe this trend will result in having
the DC-to-DC converter and capacitors in the package. Then, you would just bring one
main power to the component, and all the conversion will be made in the component
itself. It could be that PDN designers will become component designers. For instance, in
designing an SoC or a SiP, all the dies are stored on an interposer, although the interposer
is only a small PCB. So, as more components end up in the IC, it's just transferring the
same engineering challenges to the package level.
'' The trend toward
smaller, denser
designs will
continue to push
innovation."
