C h a p t e r 2
INTERCONNECT DESIGN
AND SIGNAL INTEGRITY
IN PRACTICE
As data rates climb with each successive
iteration of PCIe technology, signal
integrity becomes more important than
ever. For example, PCIe 6.0 is the first
generation to adopt PAM4 signaling
rather than NRZ, which doubles the data
encoded per clock cycle but reduces
the voltage margin between levels. The
resultant reduced signal-to-noise ratio
increases sensitivity to jitter and noise
coupling to the point where designers
need forward error correction to maintain
link stability.
At speeds of 32 or 64 GT/s, minor
discontinuities can completely collapse
Matt Burns
Global Director, Technical Marketing, Samtec
There are a lot of design variables
you can choose to optimize the
system for increased speeds.
Engineers need to rethink every
physical detail, and the system
only works when they tune the
right mix of materials, grounding,
routing, and cabling."
an eye-opening. Consequently, engineers
must now control every physical element
of the channel. Embedded systems
benefit when architectures follow clean,
short electrical paths to minimize PAM4
penalties. Therefore, designers should
consider the cumulative signal integrity
(SI) effect of connectors, PCB stack-
ups, via placements, PCB weave, routing
density, and other signal channel design
options.
Materials, Connectors,
and Cables
On the materials side, limitations in
standard FR-4 PCB materials force
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8 Experts Discuss PCIe for Emerging Embedded Systems
