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C h a p t e r 3 | S c a l i n g f r o m E m b e d d e d P C I e 4 . 0 t o D a t a C e n t e r P C I e 7 . 0 These features aid teams without sophisticated test equipment, as built- in logging shortens bring-up time and enables field troubleshooting without external analyzers. Hardware Tricks For larger platforms, retimers, redrivers, and high-speed switches bring PCIe performance into server-class edge systems. Retimers are particularly important for PCIe 5.0, PCIe 6.0, and PCIe 7.0 designs because PCB attenuation grows quickly at higher frequencies. Retimers rebuild the signal to recover clock integrity and eye margins across long or lossy paths. With strategic retimer placement, engineers can increase chances that a channel meets compliance or passes link training. For lower-cost amplification, when the design requires only modest compensation, redrivers can perform Jesse Hawkins Hardware Design Engineer, Tektronix When moving to the latest PCIe specifications, understand that not everything will be available for your system right away. It takes time for the industry to catch up. You will need to weigh your current schedule, your system needs, and what the industry can currently provide." lane shaping and limited equalization. Different than retimers, redrivers don't recover the clock or fully regenerate the signal. As such, they are a simpler, lower power, and more cost-effective solution for shorter or less lossy channels. For the best of both worlds, hybrid implementations can use high-speed switches to combine these functions with deep routing capability. In this way, designers can build multi-accelerator architectures where disparate computing elements share a common PCIe fabric. CXL ® and PCIe Finally, the emergence of Compute Express Link® (CXL) ties PCIe even more tightly to next-generation AI and memory-centric workloads. CXL extends the PCIe physical layer with protocols for shared memory, accelerator coherency, and pooled memory resources. 23 8 Experts Discuss PCIe for Emerging Embedded Systems