At higher speeds, channel loss
and reflections dominate.
Designers must think in terms
of end-to-end insertion loss, not
just trace length."
C h a p t e r 3 | S c a l i n g f r o m E m b e d d e d P C I e 4 . 0 t o D a t a C e n t e r P C I e 7 . 0
These capabilities support AI servers that need
to quickly exchange weights and parameters,
and embedded designers are now considering
CXL as a path toward memory disaggregation or
shared acceleration.
Although adoption is early, the fact that CXL
uses the PCIe PHY means it can slot into
existing hardware ecosystems. This means that
system designs can adopt CXL without replacing
foundational interconnect infrastructure.
Microchip supports PCIe scaling with
• High-speed switches that manage routing,
isolation, and load balancing in advanced multi-
domain topologies.
• Retimers that restore signal integrity and extend
reach for PCIe 5.0 and PCIe 6.0 channels.
• Link visibility and diagnostics that help
engineers validate complex paths without
specialized SI equipment.
• Architectures that let embedded platforms
incorporate GPUs, NPUs, and high-speed storage
without migrating to full server boards.
José-Augusto Moreno Escobar
Principal Hardware Engineer,
Visteon Corporation
24
8 Experts Discuss PCIe for Emerging Embedded Systems
