Issue link: https://resources.mouser.com/i/1537950
C h a p t e r 3 | I n f i n e o n ' s T o p - S i d e C o o l e d ( T S C ) Q - D P A K P a c k a g e Unlocking Switching Performance The topside cool architecture allows significant improvements in circuit layout that directly boost electrical performance. In bottom-side cool packages, the current return path must go around the device laterally, forming a large loop with parasitic inductance. This inductance limits switching speed and causes voltage overshoots that stress components and create electromagnetic interference. The Q-DPAK package allows the current return path to run directly beneath the device. This placement creates opposing magnetic fields that cancel each other out, reducing loop inductance. Lower inductance results in faster switching transitions with less overshoot and ringing—exactly what's needed to unlock the potential of wide-bandgap semiconductors. This layout optimization extends beyond the power loop. Topside cooling effectively doubles the usable PCB area compared to bottom-side cooled packages, eliminating the need for insulated metal substrate boards. All components can be mounted on standard FR4 PCBs with tighter spacing, further optimizing both the commutation loops and gate drive paths. Quantifying the Electrical Benefits The significance of optimized package design becomes apparent when evaluating actual device performance. Testing 1200 V Generation 2 CoolSiC™ devices illustrates how packaging directly influences switching behavior. Comparing devices with identical RDS(on) values in Q-DPAK versus TO-247 packages under the same circuit conditions reveals differences. The Q-DPAK enables faster dV/dt and dI/dt transitions—the key indicators of efficient switching. These faster transitions directly result in reduced switching losses, with measurements showing a 39% reduction in combined turn-on and turn-off energy losses. 15 Enabling Compact, Efficient Designs with High Voltage CoolSiC™ Discretes