Table 3 summarizes and compares the simulated ESR
2
and ESL
2
with different via placements.
In general, adding more vias reduces the PCB parasitic
impedance. However, the reduction of ESR
2
and ESL
2
is not linearly
proportional to the number of vias. The vias close to the terminal
pads give the most obvious reduction in PCB ESR and ESL.
Therefore, for hot loop layout design, several critical vias must be
placed close to the pads of C
IN
and MOSFETs to minimize the HF
loop impedance.
Table 3: Extracted Hot Loop PCB ESR
2
and ESL
2
with different via placements (Source: Analog Devices)
Case ESR
2
(mΩ) at 2MHz ESR Change Rate vs. Initial Case ESL
2
(nH) at 200MHz ESL Change Rate vs. Initial Case
Initial Case
Without Vias
2.67 N/A 1.19 N/A
(a) 1.73 −35.2% 0.84 −29.8%
(b) 1.68 −37.1% 0.82 −30.8%
(c) 1.67 −37.5% 0.82 −31%
(d) 1.65 −38.2% 0.82 −31.4%
Conclusion
The reduction of a hot loop's parasitic parameters can help
improve the power efficiency, lower voltage ringing, and reduce the
EMI. Hot loop layout designs with different decoupling capacitor
positions, MOSFET sizes and positions, and via placements were
studied and compared to minimize the PCB parasitic parameters.
A shorter hot loop path, smaller sized MOSFETs, symmetrical 90°
shape and 180° shape MOSFETs placements, and vias close to the
key components contribute to the lowest hot loop PCB ESR and ESL.
1
https://ieeexplore.ieee.org/document/310584
2
https://ieeexplore.ieee.org/document/4787289
3
https://ieeexplore.ieee.org/document/9236426
4
https://www.analog.com/en/resources/analog-dialogue/articles/4-switch-buck-
boost-controller-layout-for-low-emissions-single-hot-loop-vs-dual-hot-loop.html
Adobe Stock / logoboom – stock.adobe.com
Efficient Industrial Power with
Low EMI Silent Switcher Regulators
17
Advanced Power Solutions for Efficiency and Robustness | ADI
