Oscillation is observed in Figure 6, which supports that a high-
side, NFET switch is in a Colpitts topology.
Now let's move to a hot swap controller and see if it can be
modified to induce oscillations. A demo board is used to start into
a capacitive load. During startup, the gate voltage ramps up with a
set dV/dt, which the output follows. From the equation I
INRUSH
= C
LOAD
× dV/dt, the inrush current into the output capacitor is controlled
by dV/dt. To increase the FET's transconductance (g
m
), the inrush
is set to a relatively high value of 3A.
Test setup (Figure 7):
X UV and OV functions are disabled.
X C
TRACE
represents the trace capacitance and is a discrete 10nF
ceramic capacitor.
X L
TRACE
is a discrete 150nH inductor placed between the
LTC4260's GATE pin and the NFET's gate, representing trace
inductance.
X A 2mΩ sense resistor will limit the foldback current limit to
10A.
X A 68nF gate capacitor extends startup time to tens of
milliseconds, during which the FET is susceptible to
oscillations.
X An output capacitance of 15mF will draw amps of inrush
during startup, increasing the FET's g
m
.
X A 12Ω load provides additional current for the FET's g
m
.
Looking at the waveforms in Figure 8, once the gate voltage
ramps up to the FET's threshold voltage, the GATE and OUT
waveforms exhibit ringing. This ringing is caused by the sudden
step in the GATE waveform, resulting in an overshoot in the inrush
current. The ringing eventually subsides.
Figure 6: Scope capture showing oscillations when applying DC. (Source:
Analog Devices)
Figure 7: Simplified test circuit. (Source: Analog Devices)
Figure 8: Scope capture of decaying oscillations during startup.
(Source: Analog Devices)
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