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On the other hand, reducing the load instantly or at a fast ramp rate will give a voltage overshoot. There are also short-duration voltage glitches that can occur to the power supply due to external factors. Figure 2 shows an illustration of the different voltage transients and glitches that can be present on a power supply voltage in different scenarios. There are voltage transients that can occur in a system that are not associated with the power supply voltage but rather on a user interface, such as a mechanical switch or a conductive card for some applications. Turning a switch on and off produces voltage transients and noise on the input pin, typically a manual reset pin. All of these factors—power supply noise, voltage transients, and glitches (if excessive)—can unintentionally hit the undervoltage or overvoltage threshold of a supervisor and trigger false resets if not accounted for in the design. This can lead to oscillatory behavior and instability, which is undesirable with regard to system reliability. How do voltage supervisors address noise and transients to prevent the system from nuisance resets? There are parameters that help mask these transients that are associated with the power supply or monitored voltage. These parameters are the reset timeout period, reset threshold hysteresis, and the reset threshold overdrive vs. duration. Meanwhile, for the transients that are associated with the mechanical contact in the circuit, such as a pushbutton switch in the manual reset pin, the manual reset setup period, and the debounce time mask the transients. These parameters make the voltage supervisors robust and unaffected by transients and glitches, thus keeping the system from undesirable responses. Reset Timeout Period (t RP ) During startup or when the supply voltage is rising up from an undervoltage event and exceeds the threshold, there is an additional time on the reset signal before it deasserts, which is called the reset timeout period (t RP ). 2 As an example, Figure 3 shows that after the monitored voltage (which in this case is the supply voltage labeled as VCC) reaches the threshold from an undervoltage or startup, an added delay is present for an active LOW reset before it deasserts HIGH. This additional time allows the monitored voltage to stabilize first, masking the overshoot and ringing before enabling the system or taking it out of reset mode. The reset timeout period suppresses false system resets to prevent oscillation and potential malfunction, thus helping improve the system's reliability. Figure 2: Voltage transients and glitches that can be observed on a supply voltage in different scenarios. (Source: Analog Devices) Figure 3: The reset timeout period (t RP ) helps keep the system in reset mode while the supply voltage stabilizes. (Source: Analog Devices) Adobe Stock / Raimundas – stock.adobe.com MAX42500 SoC Power System Monitors LEARN MORE 19 Advanced Power Solutions for Efficiency and Robustness | ADI