Hot Loop PCB ESR and ESL vs. MOSFETs Size and Position
For a discrete design, the placement and package size of power FETs also have a significant impact on hot loop ESRs and ESLs. A typical
half-bridge hot loop with power FETs M1 and M2 and a decoupling capacitor C
IN
are modeled and investigated in this section. As illustrated in
Figure 6, popular power FET package sizes and placement positions are compared. Table 2 shows the extracted ESRs and ESLs in each case.
Figure 6: Hot loop PCB models: (a) 5mm × 6mm MOSFETs in straight placement; (b) 5mm × 6mm MOSFETs in 90° shape placement; (c) 5mm × 6mm MOSFETs in
180° shape placement; (d) two-parallel 3.3mm × 3.3mm MOSFETs in 90° shape placement; (e) two-parallel 3.3mm × 3.3mm MOSFETs in 90° shape placement with
ground layer; (f) symmetrical 3.3mm × 3.3mm MOSFETs on top and bottom layers in 90° shape placement. (Source: Analog Devices)
Table 2: Extracted hot loop PCB ESR and ESL with various device shapes and positions in FastHenry (Source: Analog Devices)
ESR1 (mΩ)
at 2MHz
ESR2 (mΩ)
at 2MHz
ESR3 (mΩ)
at 2MHz
ESRTOTAL
(mΩ) at 2MHz
ESR Change
Rate vs. (a)
ESL1 (nH) at
200MHz
ESL2 (nH)
at 200MHz
ESL3 (nH)
at 200MHz
ESLTOTAL
(nH) at
200MHz
ESL Change
Rate vs. (a)
(a) 0.59 2.65 0.45 3.69 N/A 0.42 2.80 0.23 3.45 N
(b) 0.59 0.3 0.38 1.27 −66% 0.42 0.09 0.17 0.67 −81%
(c) 0.24 0.27 0.83 1.35 −63% 0.07 0.07 0.52 0.66 −81%
(d) 0.44 0.3 0.28 1.01 −73% 0.25 0.09 0.08 0.42 −88%
(e) 0.44 0.27 0.26 0.97 −74% 0.21 0.08 0.07 0.36 −91%
(f) 0.31 0.27 0.13 0.7 −81% 0.12 0.07 0.02 0.21 −94%
13
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