Cases (a) to (c) present three popular power FET placements
with 5mm × 6mm MOSFETs. The physical length of the hot loop
determines the parasitic impedance. Hence, both 90° shape
placement in Case (b) and 180° shape device placement in Case (c)
result in 60 percent ESR reduction and 80 percent ESL reduction
because of the shorter loop paths compared to those in Case (a).
Since a 90° shape placement shows the benefit, several more cases
are investigated based on Case (b) to further reduce the loop ESR
and ESL. In Case (d), a 5mm × 6mm MOSFET is replaced with two
3.3mm × 3.3mm MOSFETs in parallel. The loop length is further
shortened thanks to the smaller MOSFETs footprint, leading to a 7
percent reduction of the loop impedance. In Case (e), when a ground
layer is placed under the hot loop layer, the hot loop ESR and ESL
further decrease by 2 percent compared to Case (d). The reason
is that an eddy current is generated on the ground layer, which
induces the opposite magnetic field and equivalently reduces the
loop impedance. In Case (f), another hot loop layer is constructed
as the bottom layer. If two paralleled MOSFETs are symmetrically
placed on the top layer and bottom layer and connected through
vias, the hot loop PCB ESR and ESL reduction are more obvious
because of the paralleled impedance. Therefore, smaller-sized
devices with symmetrical 90° shape or 180° shape placement on top
and bottom layers lead to the lowest PCB ESR and ESL.
The physical length of the hot loop
determines the parasitic impedance.
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14
ADI | Powering the Future
