Hot Loop PCB ESR and ESL vs. Via Placement
The vias placement in the hot loop also has a critical impact on the loop ESR and ESL. As shown in Figure 8, the hot loop with a two-layer PCB structure
and straight power FETs placement is modeled. The FETs are placed on the top layer and the second layer is a ground plane. The parasitic impedance
Z2 between the C
IN
GND pad and M2 source pad is part of the hot loop and is studied as an example. Z2 is extracted from FastHenry.
Figure 8: Hot loop PCB models with (a) five GND vias placed close to C
IN
and M2; (b) 14 GND vias placed between C
IN
and M2; (c) 6 more vias placed
on GND based on (b); (d) nine more vias placed on GND area based on (c). (Source: Analog Devices)
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