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Introduction For power converters, a hot loop PCB layout with minimum parasitic parameters can improve the power efficiency, lower the voltage ringing, and reduce electromagnetic interference (EMI). This article discusses the optimization of hot loop layout design by minimizing the PCB equivalent series resistances (ESRs) and equivalent series inductances (ESLs). Furthermore, this article investigates and compares impact factors, including decoupling capacitor positions, power FET sizes and positions, and via placements. Experiments are conducted to verify the analysis, and effective methods of minimizing the PCB ESRs and ESLs are summarized. Hot Loop and PCB Layout Parasitic Parameters The hot loop of a switching-mode power converter is defined as the critical high-frequency (HF) AC current loop formed by the HF capacitor and adjacent power FETs. It is the most critical part of the power stage PCB layout because it contains high dv/dt and di/dt noisy content. A poorly designed hot loop layout suffers from a high level of PCB parasitic parameters, including the ESL, ESR, and equivalent parallel capacitance (EPC), which have a significant impact on the power converter's efficiency, switching performance, and EMI performance. Figure 1 shows a synchronous buck step-down DC-to-DC converter schematic. The hot loop is formed by MOSFETs M1 and M2 and the decoupling capacitor C IN . The switching actions of M1 and M2 cause HF di/dt and dv/dt noise. C IN provides a low impedance path to bypass the HF noisy content. However, parasitic impedance (e.g., ESRs, ESLs) exists within the components' packages and along the hot loop PCB traces. The high di/dt noise through ESLs causes HF ringing, resulting in EMI. The energy stored in ESL is dissipated on ESRs, leading to extra power loss. Therefore, the hot loop PCB ESRs and ESLs should be minimized to reduce the HF ringing and improve efficiency. Figure 1: A buck converter with hot loop ESRs and ESLs. (Source: Analog Devices) Accurate extraction of the hot loop ESRs and ESLs helps predict the switching performance and improve the hot loop design. Both components' packages and PCB traces contribute to the total loop parasitic parameters. This work mainly focuses on the PCB layout design. There are tools for users to extract the PCB parasitic parameters, such as Ansys Q3D, FastHenry/FastCap, and StarRC. Commercial tools like Ansys Q3D provide accurate simulation but are usually expensive. FastHenry/FastCap is a free tool based on partial element equivalent circuits (PEEC) numerical modeling and can provide flexible simulation through programming to explore different layout designs, though additional coding is required. The effectiveness and accuracy of the parasitic parameter extraction in FastHenry/FastCap have been verified and compared to Ansys Q3D with consistent results. , In this article, FastHenry is used as a cost-efficient tool to extract PCB ESRs and ESLs. Adobe Stock / TKalinovskaya – stock.adobe.com How to Optimize Switching Power Supply Layout by Minimizing Hot Loop PCB ESRs and ESL By Jin ing Sun, Ling Jiang, and Henry Zhang, Analog Devices, Inc. 10 ADI | Powering the Future