Clock Tree And Timing Circuit Solutions

Circuit timing can make or break a design. While the simplest timing circuit is the best, complexity often creeps in because most contemporary applications require identical and often synchronized clock signals at some board locations and non-identical (i.e., different frequency) clock signals at others. The timing solution can rapidly turn into a multi-branched clock tree that introduces some tough design challenges.

Chief among these is meeting the design’s specification for jitter. Jitter is a measure of the variation in periodicity of a supposedly consistent clock cycle at a given component and typically increases as the clock tree becomes more complex and operational frequency increases. Worse yet, tolerances are often frighteningly narrow, sometimes as low as just a few femtoseconds (10-15s) in ultra-high speed applications. Skew, which is the difference in timing between the arrival of a supposedly synchronous signal from one component to another, can be a problem in applications employing continuous communication requiring network-level synchronization. Jitter offers a more general challenge because it affects free-running and synchronous circuits alike, and this article will focus solely on limiting its impact on timing circuit design.

Such design constraints require design engineers to select components and a timing circuit topology that not only feature high-accuracy clocks, but also ensure that the signal from those clocks travels through the circuit to the target ICs without being influenced by factors such as electromagnetic interference (EMI) or crosstalk from other signal lines. And even with careful selection of key components and efficient clock-tree design, there is no guarantee that jitter will be minimized. Manufacturing processes, supply voltages, temperature changes, and frequency variation can all affect timing performance. Testing and troubleshooting will likely be required and will typically result in component changes and even the addition of devices such as jitter attenuators to clean up clock signals to meet the product specification.

(Note: Engineers will sometimes refer to phase noise when describing clock-tree precision challenges. Jitter is a measure of timing imperfection in the time domain; phase noise is essentially a manifestation of jitter in the frequency domain. Both methods of analysis are acceptable approaches to solving the problem, although this article is restricted to time-domain techniques.)

Clock Tree Components

Timing requirements for different products are as unique as fingerprints, so there’s not a typical clock tree; however, Figure 1 shows one example of a clock tree, in this case made up of components from Silicon Labs.

Figure 1: Specialized components can produce multiple clocks from a single crystal and clock generator. The result is a clock tree. (Source: Silicon Labs)

While timing circuits exhibit widespread variety, each circuit commonly comprises one or more of the following components:

• Quartz Crystal: A piezoelectric resonator that sets the timing signal frequency.
• Crystal Oscillator: A circuit that generates multiple frequencies and outputs from a crystal frequency reference. A variant of the crystal oscillator, the voltage-controlled crystal oscillator, can be tuned to give a more precise frequency output.
• Clock Buffer: Used to distribute multiple copies of a single clock to components working from the same frequency. A variant of the clock buffer is the zero delay buffer.
• Clock Generator: An integrated circuit (IC) that generates multiple output frequencies from a single input reference frequency.
• Jitter Attenuator: An IC that “cleans” clock signals by attenuating input jitter.

Quartz Crystals

Quartz crystals (X) operate as a piezoelectric resonator, resonating at a precise frequency when an electrical signal is applied that can then be used as a reference frequency for clock generation. Crystals have some key advantages as a frequency reference:

• They can be manufactured to provide one of several specific frequencies ranging from 32kHz to 50MHz depending on how the device is cut and mounted
• The operational frequency is relatively (but not completely) temperature independent
• Crystals produce little phase noise (the frequency domain equivalent of jitter)
• They exhibit a high Q factor (i.e., the frequency output exhibits a narrow bandwidth around the nominal or center frequency).

Crystals are typically used in conjunction with oscillator circuits. The oscillator circuit enhances the temperature independence of the crystal, amplifies the crystal’s output, multiplies or divides the crystal’s reference frequency into one or more outputs of different frequencies, and changes the crystal’s sine wave output into the square wave demanded by digital circuits. The oscillator circuits are sometimes built into the target IC, or the crystal can be paired with a device known as a crystal oscillator (XO) whose output becomes the clock input for the target IC. An example is Microchip’s PL602-03, which produces low jitter and can operate with crystals operating at 12 to 25MHz to produce an output frequency of 48 to 100MHz.

Crystal Oscillators

A crystal oscillator’s square wave output can be either single-ended or differential. Differential signaling is used in high-speed—hence, more jitter sensitive—applications. Crystal oscillators are generally cost effective unless the application requires many clock frequencies or the clock precision is stringent.

An alternative to the XO for such applications is the voltage-controlled XO (VCXO). This device still oscillates with a frequency ultimately determined by a crystal, but the frequency can be adjusted over a narrow range by a control voltage. The tuning range of the VCXO is about ±100-200ppm. VCXOs are used in systems such as set-top boxes to meet the required closed-loop frequency response while maintaining a clean clock output. One example is ON Semiconductor’s NB3N508S, a low-phase noise VCXO that generates 216MHz output from a 27MHz crystal signal. The ±100ppm output adjustable range is obtained using the VIN pin and a voltage range from 0–3.3V.

Placing a crystal, XO, or VCXO next to the target IC is an inexpensive method of building a simple clock-tree for a circuit comprising relatively few timed devices. However, such an approach rapidly becomes impractical as the number of target ICs climbs.

Clock Buffers

An alternative for circuits that require multiple, identical clock inputs is a clock buffer. The clock buffer’s reference clock can come from a crystal and crystal oscillator or another clock component such as a clock generator (discussed below); from this input, the chip distributes from two to 10 copies of a clock to ICs sharing the same frequency requirements. By replacing multiple crystals and crystal oscillators, clock buffers can save board space and reduce costs by eliminating additional timing components, although with the trade-off of more complex routing. A rule of thumb is that if four or more clocks are required, it’s generally more economical to use a clock buffer than separate crystals and crystal oscillators.

At additional cost, greater precision from clock buffers can be gained from employing a zero delay clock buffer. Zero delay buffers, for example IDT’s 9DBL0, a 3.3V, dual-output chip targeted at PCIe applications, fan out one clock signal into multiple clock signals with no delay and low skew between the outputs. The devices employ a phase locked loop (PLL) that uses a reference input and a feedback input driven by one of the outputs. The phase detector inside the PLL adjusts the output frequency of a VCXO such that its multiple outputs have no phase or frequency difference, and hence no jitter difference.

Clock Generators

Like clock buffers, the reference frequency for clock generators can be supplied by a crystal and crystal oscillator or another timing device. However, whereas clock buffers simply reproduce multiple copies of the same timing signal, clock generators can generate multiple output frequencies from a single input reference frequency. The devices might also incorporate other features, including turning outputs on and off, intentional frequency skewing, and spectrum spreading. Differential signaling, skew control, careful transmission line design, and other techniques can ensure that a centralized clock source provides similar precision to multiple discrete crystals and crystal oscillators.

An example of a clock generator is Silicon Labs’ Si5338Q chip, a high-performance, low-jitter clock generator capable of synthesizing four independent user-programmable clock frequencies up to 350MHz and select frequencies up to 710MHz. The output drivers support four differential clocks, eight single-ended clocks, or a combination of both (Figure 2).

Figure 2: Clock generators produce multiple output frequencies from a single crystal reference frequency input, saving on component count. (Source: Silicon Labs)

Jitter Attenuators

Another component that might be required in a clock tree is a jitter attenuator. Jitter attenuators are specialized components that are sometimes employed to “clean-up” a clock signal in high speed applications when jitter must be reduced to negligible levels to ensure that the circuit operates satisfactorily.

Jitter Defined

Jitter is a measure of the variation in periodicity compared with a “perfect” clock and is measured in seconds (s).

Types of Jitter

Jitter comes in two forms, random and deterministic:

Random Jitter

Random jitter is essentially the system’s intrinsic noise. The noise follows a broad Gaussian curve and can’t be correlated to an identifiable noise source, making it difficult to diagnose. Fortunately, in most systems random jitter is negligible and doesn’t affect circuit performance. However, on occasion the noise floor may be high enough that some troubleshooting will be required to improve circuit performance.

Deterministic Jitter

Deterministic jitter has a specific cause and is typically repetitious. This makes tracking down the cause somewhat easier than random jitter. Deterministic jitter can be further classified as periodic or data-dependent. For example, jitter caused by a switching power supply is deterministic and periodic, matching the operational frequency of the power supply. In contrast, data-dependent jitter can be periodic or aperiodic because it’s caused by factors such as the dynamically-changing duty cycles and irregular clock edges of a coded serial data stream from Ethernet or PCIe systems. Data-dependent jitter measurement varies by system, functionality, and other factors and can be difficult to diagnose.

To further complicate troubleshooting, some deterministic jitter may appear to be random because several noise sources overlap one another, masking the individual-correlated noise sources.

Jitter Metrics

Jitter can be measured in three forms: Absolute, period, and cycle-to-cycle.

Absolute Jitter

Absolute jitter—also called or time interval error, (JTIE)—is the difference in the position of a clock's leading edge from where it theoretically should occur, according to a perfect clock.

Period Jitter

Period jitter (Jper)—not to be confused with periodic jitter described above—is the difference between the longest and shortest clock cycles for all individual clock cycles over a fixed number of cycles, typically 1,000 or 10,000 (Figure 3).

Figure 3: Period jitter is the difference between the longest and shortest clock cycles over an extended observation. (Source: Silicon Labs)

Cycle-to-Cycle Jitter

Cycle-to-cycle jitter (Jcc) is the maximum difference between consecutive clock periods measured over a fixed number of cycles, typically 1,000 cycles or 10,000 (Figure 4).

Figure 4: Cycle-to-cycle jitter is the maximum difference between consecutive clock periods measured over an extended observation duration. (Source: Silicon Labs)

Jitter Effects

Some jitter is inevitable and not all bad. However, excessive jitter will compromise circuit performance. For example, high-end systems running at high frequencies and requiring precisely-synchronized timing will include a tight specification for JTIE. Examples include Synchronous eEhernet (SyncE) and optical transport networking (OTN) applications. High JTIE will cause loss of synchronization and failure of these advanced systems.

Jper and Jcc are important for most digital applications because they can, for example, affect the set-up and hold time of latches and flip flops in digital systems:

• Latches transfer data when the clock is high and hold the data when the clock is low.
• Flip-flops transfer data on the rising edge of a clock cycle.

If the data stream and system clock are affected by Jper and Jcc, they can in turn affect the set-up and hold times of latches and flip flops, causing data to be corrupted or lost, reducing the sampling precision of ADCs, or imposing limits to processor operational frequency. Control over Jcc is also important in applications that are unable to tolerate sudden changes in clock frequency (Figure 5).

Figure 5: Excessive jitter can cause sampling and hold problems resulting in lost or corrupted data. (Source: IDT)

Solutions for Timing Problems

Applying these practices and techniques will help solve timing problems:

Adopt Good Design Practices

Limiting timing problems starts with keeping things as simple as possible. No matter how high the performance of each timing component, each device will introduce some intrinsic jitter and the effect is cumulative. Fewer devices typically result in lower overall jitter.

The product designer should avoid including a tight specification for jitter if not warranted. Identifying and limiting jitter is a difficult and time-consuming process and should only be undertaken if vital—every circuit can tolerate some degree of jitter without performance compromise.

This advice extends to the operational parameters of the circuit. The developer should review requirements such as operational frequency because the higher the frequency, the higher the magnitude of Jper and Jcc. (JTIE is independent of operational frequency.)

The developer should also consider the best topology for his or her clock tree. Cost can be reduced by using fewer crystals and clock generators and adding more clock buffers but at the tradeoff of timing precision. Similarly, timing precision can be increased by employing VCXOs and zero delay buffers at the trade-off of increased complexity (and potentially longer lead times because components such as crystals tend to be in demand).

Other established design techniques include these:

• Limiting clock tree latency by keeping signal lines short, choosing the optimum topology, and selecting the best components the material budget can support.
• Controlling transition times to keep clock edges well defined.
• Matching components throughout the circuit (for example, use the same type of clock generators and clock buffers unless a different type is required for operational reasons).
• Matching clock line lengths when distributing multiple signals from a single component.
• Using spacing and shielding to protect clock lines from crosstalk.
• Using clock buffers with integral decoupling.

The developer should also take advantage of the vast, free library of vendor white paper and application notes on timing circuit design for advice.

Finally, the developer should work out tolerances and jitter accumulation based on schematics of clock-tree topologies and selected component datasheets. Many silicon vendors offer online tools to simplify this process and assess the impact of both component and topology trade-offs. The tools can even be used to suggest components and topologies for a given application.

Analyze the Clock Tree

Following good design guidelines, selecting the appropriate clock-tree topology, and employing high-quality components are good practice but won’t guarantee satisfactory timing performance. Many other factors exist that can introduce jitter such as unmatched signal line lengths, EMI, voltage fluctuations, and even mechanical stress (affecting the piezoelectric characteristics of the crystal) that are impossible to predict. These sources of jitter can compromise performance of even the best-intentioned timing circuit.

If the timing circuit performance is not as expected, careful analysis using instrumentation designed for the purpose is required to pin-down the source of the timing problems.

Each type of jitter is measured and specified in picosecond (or femtosecond for timing systems requiring high levels of precision) deviations from the perfect clock. Larger deviations indicate lower quality timing. Jitter is also commonly specified in root mean square (RMS) values of the timing increment. Calculating RMS values typically assumes a Gaussian distribution of timing deviations and the calculated result is the standard deviation of the jitter measurement (Figure 6).

Figure 6: Jitter is commonly specified in an RMS value that defines the standard deviation of the Gaussian distribution of timing deviations. (Source: IDT)

Jitter measurement (a time domain value) is typically performed by high-speed digitizing oscilloscope. The instruments can directly measure JTIE, Jper, and Jcc and enable the measurement of jitter at high- or low-frequency clock signals. Oscilloscopes are particularly suitable for measuring data-dependent jitter (Figure 7).

Figure 7: High-speed digitizing oscilloscopes are the best instruments for analyzing jitter. (Source: Silicon Labs)

By post-processing the raw data, the RMS jitter value can be calculated. The RMS jitter value can then be converted to a peak-to-peak value by first calculating a “crest factor.” The crest factor calculation typically assumes an industry standard bit error rate (BER) for clocks of 10-12. For this BER, the RMS to peak-to-peak crest factor is 14.069. Consequently, an RMS jitter value of 1ps equates to a peak-to-peak jitter of 14.069ps.

If the magnitude of measured jitter is outside of the specification, some skill is required in the use of instrumentation, not only to determine the magnitude of jitter, but also to determine its source. Periodic deterministic jitter is the easiest to track down with data-dependent jitter but more difficult to troubleshoot. Harder still is periodic or data dependent jitter resulting from overlapping sources, as this type of jitter can have the appearance of random jitter. For particularly tricky problems, advice should be sought from the instrumentation and silicon vendors.

Improve Timing Circuits

Many design techniques can be used to resolve jitter problems once the source of the problem has been established. Depending on the source of jitter, the problem can be resolved by simplifying the circuit by

• Replacing several buffers with one that offers the same number of outputs as the others combined
• Swapping components for higher-specification or specialist-operation devices
• Rerouting and matching circuit trace lengths.

The specific solution will depend on the type of jitter and its source.

In a system where random jitter is the major contributor to poor performance, the best approach is to simplify the clock circuit to as few components as possible and then methodically replace each of those components in turn with a higher specification chip until the noise floor is lowered to an acceptable level.

Other areas can be improved as well, including the switching power supply and the target IC:

Switching Power Supplies

One area that often reveals to be the source of both random and deterministic jitter is the power supply. In particular, switching power supplies are popular because of their high conversion efficiency, but they’re also notorious sources of EMI and other noise. Such noise should be filtered from the supply’s output; otherwise, it can compromise clock signal integrity. Also, the designer should also ensure the power supply output traces don’t pass too close to timing circuit lines to limit the chance of crosstalk; the same is true of other signal traces. A good design tip is to run a ground trace next to the clock lines, or if that’s not feasible, increase the spacing between clock lines and other signal lines.

Target ICs

Another common problem area is trace termination at the target IC. Without proper termination, impedance mismatches will occur and energy will be reflected down the line. These pulses may be large enough to falsely trigger a device input, leading to improper (and potentially catastrophic) circuit operation. The most popular form of termination for a timing circuit uses a resistor placed in series with the signal line as close to the source as possible. The resistor value is selected to match the output impedance of the clock driver to the impedance of the trace. The resistor then absorbs energy returning along the signal trace before it can affect the timing chip.

Use Jitter Attenuators

Sometimes jitter can’t be brought within specification even when all troubleshooting techniques have been exhausted. When this happens, one option is to employ jitter attenuators in the clock tree to clean up the timing signal. Devices such as IDT’s 8V19N407 or Silicon Lab’s Si5317 use a PLL architecture to facilitate jitter attenuation (and often frequency multiplication). The PLL is used to filter noise from the input clock and produce a low jitter output clock. Reducing the loop filter bandwidth increases the amount of jitter attenuation on the reference clock, transferring less jitter from the input to the output (Figure 8).

Figure 8: Jitter attenuators employ PLLs to filter noise from the input clock and produce a low jitter output clock. (Source Silicon Labs)

Conclusion

Controlling jitter starts with a clock-tree schematic and selection of circuit components. Many of the choices are dependent on the application. Developers should take advantage of silicon vendors’ online resources to estimate timing circuit performance before committing to hardware design. This can save time and cost later in the design process and can simplify the component selection and procurement.

However, even after taking advantage of online resources, adopting established design techniques, and carefully selecting chips, there is no guarantee that jitter will meet the limits implied by the component data sheets. Many other influences on the timing circuit can introduce unwanted noise. Testing and troubleshooting will almost always be required.

Analyzing and eliminating jitter is not a trivial process. However, adopting good design principles, selecting quality components, checking circuit performance with the proper instrumentation, and adopting a methodical approach to resolving any problems identified in the analysis typically results in a satisfactory outcome. Failing this, the developer is advised to turn to the timing component vendors. Virtually all reputable companies offer design and troubleshooting services and the experience gained by the developer can be applied to the next timing circuit project.