Combining RISC-V and FPGAs Offers New Design Solutions

By Jim Harrison for Mouser Electronics

Application Areas For RISC-V

RISC-V-based processors can be used in various applications, including imaging and sensor interface, military and aerospace, IoT, automotive and rail transportation, and industrial controls. RISC-V designs offer high-data throughput that is needed across several applications, including smart embedded vision, hybrid and electric vehicles, wireless communication infrastructure, and robotics.

The processors’ immunity to network-based security attacks is not something one can easily find with other cores/ISAs, especially when it comes to IoT applications. Instead of relying only on compartmentalization and communication security, RISC-V is unique in that it includes computing security to stop buffer overflows and protect the processor from being overtaken by cyberattacks that arrive via the network and exploit vulnerabilities in the code.

Some RISC-V implementations feature high reliability and resources for safety-critical and mission-critical designs. In addition, there are two working groups currently discussing security extensions to the base ISA, one for cryptographic extensions and the other for a trusted execution environment.

Other examples of available application specific extensions would be a finite impulse response (FIR) Filter, a CRC32 (32-bit cyclic redundancy check), and 3DES (Triple Data Encryption Standard) algorithms. By adding these extensions to a RISC-V core, performance on these functions can be greatly accelerated while saving considerable amounts of power.

Implementation Examples

Microsemi/Microchip offers RISC-V soft cores for two FPGA families (plus one rad-tolerant type). Their Mi-V RISC-V ecosystem includes FPGA soft-core and SOC hard-core implementations.

The IGLOO2 FPGA offers 5K to 150K LEs with a high-performance memory subsystem, up to 512KB embedded flash; 2 x 32KB embedded SRAM, two DMA engines, and two memory controllers. You can implement up to 16x transceiver lanes for Peripheral Component Interconnect (PCI) Express Gen 2, XAUI / XGXS+, or Generic ePCS mode at 3.2G. There are up to 5 Mbits of SRAM, 4 Mbits eNVM, DSP blocks, and hard 667Mbps DDR2/3 controllers. All this with standby power consumption as low as 7mW.

The low-cost M2GL-EVAL-KIT makes it easier to develop embedded applications that involve motor control, system management, industrial automation, and high-speed serial I/O applications using IGLOO2. The kit provides a platform to develop transceiver I/O-based FPGA designs to build PCI Express and Gigabit Ethernet-based systems. It is small form-factor PCIe compliant which allows quick prototyping using any desktop PC with a PCIe slot.

PolarFire is a mid-range FPGA family that carries on in the 100k to 500k logic element size range. The devices have four to twenty-four optimized 12.7 Gbps transceivers that are said to take 1/2 the power vs. competing products, plus DDR4 and 1.6 Gbps LVDS interfaces. Integrated hard IP includes a dual PCIe endpoint/root port and a crypto processor. The chips offer a system controller suspend mode for safety-critical designs and many security features.

Microchip/Microsemi’s PolarFire Video Kit (MPF300-VIDEO-KIT-NS) offers a high-performance evaluation mechanism for 4K image processing and rendering using dual camera sensors as well as numerous display interfaces. The kit demonstrates popular imaging and video protocols, including MIPI CSI-2 TX, MIPI CSI-2 RX, HDMI 1.4 TX, HDMI 2.0, DSI and HD/3G SDI. With a 300K LE PolarFire FPGA, DDR4, and SPI-flash, the kit is ideally suited for low-power mid-bandwidth imaging applications.

Security Features and FPGA Configurations

Security features for these FPGAs includes differential power analysis (DPA) bitstream protection, a physically unclonable function (PUF), 56 Kbytes of secure eNVM, tamper detectors and countermeasures, digest integrity check for FPGA, μPROM, and sNVM, a true random number generator, and a CRI DPA countermeasure pass-through license. Memory supports single-error correction and dual-error detection. The CPU designs are immune to Spectre- and Meltdown-style attacks and the built-in crypto processor is immune to side-channel attacks. The core designs were developed in conjunction with SiFive and UltraSoC.

Implementing a RISC-V soft processor in either device uses 10k gates in base configurations and 26K gates in a version with single precision floating point (see figure 3). Users can start designing today using the Libero® SoC 12.3 FPGA design suite and the Eclipse-based SoftConsole 6.2 IDE for the embedded developer. Designers can even debug their embedded applications today using Renode by Antmicro —a virtual model of the microprocessor subsystem.

Another Softcore Example

Another example of a great FPGA/RISC-V combo is the Lattice Semiconductor RISC-V MC CPU soft IP with a 32-bit processor core and optional timer and programmable interrupt controller (PIC). The CPU core supports the RV32I instruction set, external interrupt, and JTAG, GDB, and OpenOCD debug. It has five stages of pipelines and support for the AHB-L bus standard.

The chip design is implemented in Verilog HDL, using Lattice Propel Builder software. It can be targeted to the CrossLink-NX device with 2.5 Gbps Hardened MIPI D-PHY, 5 Gbps PCIe, 1.5 Gbps programmable I/O, and DDR3 interfaces or the MachXO3D high security FPGA with hardware root-of-trust and dual boot and 4300 or 9600 LEs.

High-Performance RISC-V Hard-Core Processor

Microchip/Microsemi has also introduced a hard-core version of RISC-V processing and it has five cores four processor cores and a monitor core all of which are RV64 64-bit implementations. The SoC has a PolarFire FPGA fabric with an 18 x 18 MACC, PLLs, and DLLs.

It's the first system-on-chip (SoC) FPGA with a deterministic, coherent RISC-V CPU cluster and a deterministic L2 memory subsystem enabling Linux and real-time applications. The PolarFire SoC yields 6.5k Coremarks @ 1.3W.

There are five versions of the chip. The MPFS025T version has 23k logic elements, 68 math blocks, and four 12.5 Gbps SERDES lanes. The MPFS460T is the largest version, with 461k LEs, 1420 math blocks, and 20 SERDES lanes.

Figure 1: The powerful five-core PolarFire SoC (system-on-a-chip) FPGAs come in four versions with package sizes from 11 mm to 16 mm square. (Image Courtesy Microchip)

The PolarFire SoC Icicle Kit is a low-cost development platform for evaluation of the five-core Linux capable RISC-V microprocessor subsystem. It features onboard memories (LPDDR4, SPI, and eMMC flash) to run Linux off-the-shelf and a multi-rail power sensor to monitor various power domains.

Conclusion

As we said at the start, there’s less risk using RISC. For a smart design team, the RISC-V ISA could be used to establish an MCU framework that spans generations of devices and products. And, for really demanding applications, the hard implementations with FPGA fabric and cores with vector extensions (RVV) are becoming readily available.

The new way of doing things is to pick an instruction set first, then pick a vendor or build your own core, and then add extensions as needed. Remember, RISC-V is not a core or a CPU it is an instruction set specification. You can get a core that’s part of an FPGA, get a core design from multiple open source vendors (at least a dozen), or buy a core/processor from commercial core providers.