RISC-V Open Source Processors

For Your Next Embedded Design

By Jon Gabay for Mouser Electronics

Reduced Instruction Set Computers (RISC) are not new architectures and have been around for decades as a streamlined alternative to the Complex Instruction Set Computers (CISC) that preceded them. Older CISC processors worked very well and for the most part followed a Von Neumann architecture where a processor’s code would operate in cycles to fetch, decode, and execute the instructions. RISC processors on the other hand follow a Harvard architecture where the instruction code bus is separated from the data bus allowing simultaneous access that lets the processor perform each instruction in a single cycle. This makes them fast, deterministic, and easier to create compilers and libraries of functions that could more easily port from machine to machine.

But, like CISC processors, different manufacturers have different internal architectures, peripherals, I/O, and instruction sets. This requires development tools tailored to the specific manufacturer and parts in order to develop a design. Development tool makers deal with this by maintaining different “plug-ins” and header files for the development tool chains for each processor. Quite a task.

Although the RISC-V project began in 2010 at Berkeley, CA, with both Berkeley and non-Berkeley experts and contributors, it’s been only since 2018 that RISC-V has gained more attention from processor manufacturers and design engineers since it holds the promise of freeing designs from being locked into a manufacturer’s part or family of parts.

RISC-V is an open specification for an Instruction Set Architecture (ISA) that allows any manufacturer to make a processor that will run the same code.  This Open Source instruction set approach eliminates the need to learn and create unique development ecosystems for each processor’s architecture. In addition to dedicated processors, the RISC-V cores can be used in ASICs and FPGAs for even higher integration.

Key is that the uses of open-source RISC-V instructions are layered and extensible. This means that using the opens source standard instructions set still allows the creation of Application Specific Instruction-set Processors (ASIPs) by letting designers add their own instructions that perform deeply embedded functions more efficiently. This can take the form of chip maker’s extensions that differentiate themselves or as ASIC/FPGA hardware from the mind of design engineers everywhere. EDA vendors can support extensions through Verilog or VHDL for example.

Why is the timing of this so important you may ask? The Advanced RISC Machine (ARM) architected processors are the dominant RISC force in the market today, but, because of several factors like the ARM/Chinese joint venture with Huawei and the pressure leveraged by major EDA core processor offerings, ARM revenues are steadily declining and the persistent worry of increased ARM licensing costs change the feasibility equations.  ARM is raising its prices quite a bit. It is not uncommon for a company to pay six-figure licensing fees up front as well as very high-cost royalties.

Political friction over high tech issues with communications and mission critical technologies are pushing all sides towards the open sourced RISC-V architecture. To avoid geopolitical friction, the international pressure has made the Open Source RISC-V an international standard, and in March officially became RISC-V International and is headquartered in Switzerland instead of the US.  The RISC-V foundation (riscv.org), maintains the standard. 

Figure 1: RISC-V. Image Source: RISC-V

Architecture

RISC-V uses a standard 5-stage pipeline and allows up to two instructions per clock cycle execution.  A standard Load/Store architecture is implemented which differentiates ALU from Memory operations.  Defined as a Base Integer ISA, a base register adds the offset register value and works with the source or destination register to allow complete access to external memory. I/O can be mapped into this space for flexible programmed I/O and block operations.  A Load-Reserved/Store-Conditional instruction (LR/SC) is a useful instruction that allows updating or outputting depending on conditional criteria.

Base Integer instructions are characterized by integer register widths and the size of the user design space.  The RV32I and RV64I instruction variants support 32- and 64-bit user level address spaces, and a future RV128I is intended to be added for flat 128-bit addressing capacity.

The instruction set intent is to allow native hardware implementation without “over-architecting” to keep it well-positioned to be implemented as an ASIC or FPGA. Instruction variants include both 32- and 64-bit addressing capabilities and user level ISA extensions and specialized variants are supported.

The little Endian configuration is used like the x86 architectures for example, and accessed memory addresses do not have to be aligned to their word width which can be 16, 32, 64, or 128 bits. A “Fence” instruction assures that preceding instruction value results are visible for other threads or I/O devices. This separates memory read or write operations without affecting I/O eliminating wait times.

Helpful is the memory upper load immediate instructions that allow the upper 20 bits of the 32-bit address register to be loaded with immediate data values placed into the single cycle instruction.  Another memory address manipulation instruction allows setting the lower 12 bits. This helps create position independent code letting programs generate 32-bit addresses relative to the program counter register.  While 128-bit addressed memory seems unfathomable today, the capability exists. 

Included in the 32 Integer register set are stack, global, and thread pointers. Another 32 floating point registers are also available for arguments, parameters, and results.  Register x0 always returns a “0” when read and is common in all implementations. Note that RISC-V has a 16-bit variant for embedded applications as well as the 32-bit flavor for both integer and floating point register sets.

RISC-V allows 16, 32, 48, 64, and 80+x bit- length instructions. Variable length instructions are supported and reserved encoding for greater than 192-bit instruction lengths is included in the present specification.  Exceptions, Traps, and Interrupts are fully supported.

Arithmetically, as expected, both integers multiply and divide are supported using standard extensions, in this case “M.” Single-precision (“S”) and double- precision (“D”) operations add floating point (“F”) extensions, and a class of Atomic operation extensions (“A”)  are defined as well. A Quad precision (“Q”) extension is also provided and standard extensions for decimal notation (“L”) are supported as well.

Variations and Vector Processing support a range of data parallel accelerators as an explicit goal of the RISC-V architecture.  A relaxed memory model will make it easier for future extensions to work with data parallel coprocessor or accelerator functions more easily. For example, a user-defined accelerator may be designed to run kernels from important application domains. Here, you can eliminate all but base integer operations and use only extensions that make the task at hand run more efficiently.

This can be useful for AI acceleration and machine learning. Work is being done to increase teraFLOPS/Watt using Domain Specific Extensions (DSEs), Tensor instructions, and Vector ISA. User- defined hardware accelerators will always outperform software-based calculated solutions, and these custom accelerators can be chained into the data pipeline and also accelerate graphics, multimedia, DSP, real-time motor control, and other specific architectural requirements.

While accelerators are good for hardware and computer-intensive tasks, hypervisory instructions are especially useful when it comes to implementing virtual machines as guests or processes. The internally embedded processes can handle intensive or housekeeping tasks and be part of a processor’s code or offloaded to other cores in the system. Using the “H” extensions, hypervisory instructions are part of the privileged instruction sets that let a processor running in machine mode have multiple users, processes, and supervisors.  Planned as an orthogonal implementation, configuration bits can allow supervisory code to access hypervisor registers or generate interrupts upon access.

Explicit definitions for hardware threads are part of the privileged instructions which allow recovering from a stalled thread or a thread that is not ready to proceed (waiting for input or in the middle of a calculation for example). Hardware threads can also implement more efficient interrupts since save and restore operations don’t have to be implemented for fast and real-time service routines.  Five modes of hypervisory operations are supported with RISC-V’s ISA. These are machine, supervisor, user, supervisor-under-hypervisor, and user-under-hypervisor.  This leaves a lot of flexibility for multiple independent processes to be running without stepping on each other.

Development

Fortunately, several quality development environments, boards, and kits are readily available from stock for RISC-V development.  While few have introduced discrete chips, several hard and soft cores can be leveraged to begin evaluation and development of the attainable performances RISC-V promises. 

As a discrete chip, the first RISC-V chip comes from the Chinese T-Head design group

which introduced its XT910 based on a 64-bit core implementation of the RISC-V architecture.  The XT stands for Xuantie which translates into Heavy Sword made from dark iron. 

This first dark iron sword stab at implementing the RISC-V as a discrete chip (RV64GCV) features 1, 2, or 4 cores per cluster, and a vector engine for AI acceleration. Aimed at edge servers, AI, and industrial control, and is fabricated using a 12-nanometer FinFET process from Taiwan Semiconductor. Each core contains 32K or 64K of both L1 data and L1 instruction cache and can sync multiple cores for faster memory access. Using a 2.5 GHz clock and all four cores cranking away, the XT910 is touted as performing at 300 GFLOPs. This is taking aim at the large 175 Zetabyte data sets anticipated by 2025.

The first touted development environment for RISC-V was announced by SiFive. This is a company entirely focused on the new architecture. Its release of the $999 RISC-V developers’ board sold out in a matter of days. It only took a month for Western Digital to ink a multi-year license for SiFive’s Freedom Platform, and Western Digital announced that it plans to move its entire product portfolio to RISC-V silicon and became an investor in SiFive.

Available now as a chip or on a development platform is the newer Crowd Supply HiFive FE310-G002 32- bit RISC-V SoC and development board.  The 3.3V development board features a 32-bit wide data bus and integrated wireless technology for networking and IoT applications requiring high-end processing power.

Developing the RISC-V based products as a core provides the highest possible integration and the highest possible performance since most all functions and data transfers can take place monolithically.

While the use of a hard core should provide a fully characterized and debugged processor starting point, soft cores allow user-integrated functionality to live side-by-side monolithically.

Terasic provides a core-based development platform targeting RISC-V. The PO633 development  tool centers around the 500-pin 50,000 logic element Intel/Altera MAX 10 FPGA. This features internal nonvolatile instant-on memory, DSP blocks, and external DDR2 and DDR3 DRAM interfaces.

As a generic processor engine, virtually any operating system can be implemented, and even multiple operating systems can coexist within a runtime environment as a virtual machine being emulated by the high-performance core’s processing power.

It is interesting to note that the recent release of Linux 5.8 supports RISC-V architectures, meaning a license-free hardware and operating system solution is out there for designers to use.

Conclusions

To date, first-generation discrete chips and cores are available now to develop with. As platforms for learning and experience, this can give designers a head start in gaining familiarity with the architecture and tools.

Expect to see more players in the field. Also expect to see some real products starting to emerge based on the RISC-V architecture. The enticement of free core licensing and even free OS licensing will be a large driver of high-volume and high-performance designs at low RISC.