Chiplets Are Sparking an IC Design Revolution
Image Source: Node Connector/stock.adobe.com; edited by Mouser
By Alistair Winning for Mouser Electronics
Published June 19, 2026
For years, system-on-chip (SoC) design has been the path to higher integration. This path has been somewhat guided by the industry’s need for smaller and faster devices that maintain superior power efficiency. While equipping a single die with more functionality has helped meet those demands and simplified system design, as things get more complex and process nodes become more specialized, that approach is showing its limitations.
Chiplets offer a different path forward, breaking monolithic designs into modular building blocks that can be combined within a single package. These integrated devices have evolved from discrete integrated circuits (ICs) and simpler application-specific integrated circuits (ASICs) or application-specific standard products (ASSPs) toward increasingly complex SoCs. ASICs, ASSPs, and SoCs all have one thing in common: They are fabricated on a single wafer using a single semiconductor process.
This approach offered clear benefits, such as reduced size and faster time to market, but it also introduced new drawbacks that have become more pronounced as technology has advanced. The process of stitching together different pieces of intellectual property (IP) into a single entity is complex, and this complexity increases as larger, more complex functions are incorporated into SoCs. There is no guarantee that the desired IP block will be available and optimized for the specified fabrication node, which can delay optimization or require a compromise to choose a different IP block to keep the project on schedule. Since the ICs are fabricated using a specific manufacturing process on a single node, if a developer were to integrate an IP block that required a different process (e.g., a power circuit), the whole chip would have to be built on the larger node. This would hinder the performance of the digital sections and be much less efficient.
As more functionality is added, yields decrease because a single defect can render a larger portion of the wafer unusable, thereby increasing costs. At the same time, emerging technologies—such as wide-bandgap semiconductors, including silicon carbide (SiC) and gallium nitride (GaN)—cannot be easily integrated into traditional monolithic SoC designs, limiting the ability to take full advantage of their efficiency and performance benefits.
Chiplets Address the Limitations
The drawbacks have slowed the process of designing SoCs and made them more expensive, but that hasn’t deterred widespread adoption because the benefits they offer ultimately outweigh the downsides. These limitations have led to the development of chiplets as an alternative approach to system integration.
Chiplets integrate different dies together into a single package. They allow IP blocks fabricated on different process nodes to be integrated within a single package. Splitting functionality into smaller, simpler dies improves yields and gives designers more assembly flexibility. This approach also enables the integration of technologies that are difficult to integrate into advanced nodes, including wide-bandgap power devices and photonics.
Along with lower costs enabled by higher yields, chiplets lower the barrier to entry into new businesses. In some cases, they can also reduce upfront design costs through reusable IP. Organizations can choose the IP blocks they need and connect the dies through a package-level interconnect, such as an interposer (Figure 1). Also, using proven dies that already meet the qualifications for specific industries or functions makes accreditation much simpler (e.g., meeting ISO 26262 requirements, including Automotive Safety Integrity Levels (ASILs)).
Figure 1: Instead of stitching IP blocks into a monolithic design, chiplets take the IP blocks individually and make them work together. (Source: imec; used by permission)
Using chiplets also helps reduce design risk when integrating cutting-edge fabrication technologies. These designs are expensive, generally have a lower yield, and are very time-consuming when crafting a full SoC. Chiplets allow the designer to use the latest fabrication technologies only where needed and most beneficial. The other chiplets in the design can use reliable, proven, and less expensive nodes to provide the optimal balance of performance, size, efficiency, and cost.
For example, a chiplet design could include artificial intelligence (AI) accelerators fabricated on the latest highest-performance technology, a GaN power distribution chiplet to deliver power efficiently, standard communication chiplets on older geometries to offer proven solutions and keep costs acceptable, and high-density 3D memory chiplets to save space and boost performance. Such a design would be a complete system in a single package, which could never be achieved on a monolithic die (Figure 2).
Figure 2: Chiplet vs. monolithic die approach performance and cost comparison. (Source: Keysight)
Chiplet-based designs also make it easier to create product variations and performance upgrades when new chiplets become available. If teams are developing their own IP, they can split functionality across chiplets to enable parallel development and reduce overall design time.
Though the theory sounds ideal, putting it into practice is often much more difficult. There were initially major obstacles, including communication between the chiplets. To make chiplet-based solutions competitive, communication performance—especially speed and latency—had to be comparable to that of integrated communication between IP blocks in SoCs.
This requirement is especially true at the beginning of this chiplet revolution. Initially, the idea was developed by larger multinational companies, such as Intel and AMD, for customers like Google and Meta that were heavily invested in AI. These organizations have the engineering, time, financial resources, and IP libraries to develop their own methods of implementing chiplet-based designs. However, reaching the wider market and unlocking the full potential of chiplets required standardization, especially for high-speed, low-latency interconnects that enable seamless communication between chiplets that are built on different processes.
To achieve this, a group of semiconductor manufacturers and major customers formed a consortium to develop an open standard for high-speed, low-latency chiplet communication. The result of that collaboration was the introduction of the Universal Chiplet Interconnect Express (UCIe) standard in 2022. UCIe defines the physical layer and the die-to-die adapter, as well as the protocol layers that enable chiplets to access commonly used protocols, such as Compute Express Link (CXL) and PCIe. The consortium has grown to more than 140 member companies, and the standard continues to evolve.[1]
2.5D vs. 3D Chiplets
While standards such as UCIe address communication between chiplets, physically integrating those dies introduces additional design considerations.
There are currently two main types of chiplet-based SoC designs: 2.5D and 3D. The 2.5D design typically places chiplets horizontally adjacent to each other on a silicon interposer, providing the dense wiring interconnects needed for communications. The 3D design stacks the chiplets on top of each other.
Each approach has its own set of trade-offs. In 2.5D implementations, chiplets are spread across a silicon interposer, which creates more predictable thermal behavior. The architecture is also easier to design, test, and manufacture than 3D and comes with a more mature supply chain. It offers greater flexibility in supporting different process nodes, making it well-suited for high-performance computing, large networking SoCs, and AI accelerators. However, relying on an interposer can increase costs and introduce routing complexity.
In 3D implementations, chiplets are stacked vertically and connected with through-silicon vias (TSVs) or hybrid bonding (Figure 3).
Figure 3: 3D technology stacks chiplets vertically, shortening interconnect lengths and increasing performance. (Source: UCIe Consortium Specification, used by permission)
Since stacking reduces interconnect distance, it enables higher performance, lower latency, and better power efficiency. However, stacking introduces thermal challenges because heat becomes more difficult to dissipate across the vertical dies. Despite these challenges, 3D chiplets are gaining traction in compact, high-performance applications, such as edge devices, low-power compute modules, and mobile and augmented reality and virtual reality (AR/VR) systems.
Conclusion
Chiplets provide a practical path forward as monolithic SoC designs face more limitations. Their ability to combine dies optimized for different processes with better yield, while supporting modular development, makes them a good fit for more complex system requirements. As these demands continue to grow, chiplets are positioned to become a foundational element of next-generation semiconductor systems.